A Small-Area Self-Biased Wideband CMOS Balun LNA with Noise Cancelling and Gain Enhancement

Erik Bruun; Pietro Andreani; J. R. Custódio; J. Goes; J. P. Oliveira; L. B. Oliveira

A Small-Area Self-Biased Wideband CMOS Balun LNA with Noise Cancelling and Gain Enhancement

Erik Bruun, Pietro Andreani, J. R. Custódio, J. Goes, J. P. Oliveira, L. B. Oliveira

Research output: Chapter in Book/Report/Conference proceeding › Article in proceedings › Research › peer-review

Abstract

In this paper we present a low-power and small-area balun LNA. The proposed inverter-based topology uses selfbiasing and noise cancelling, yielding a very robust LNA with a low NF. Comparing this circuit with a conventional inverterbased circuit, we obtain a ∼3 dB enhancement in voltage gain, with improved robustness against PVT variations. Simulations results in a 130 nm CMOS technology show a 17.7dB voltage gain, nearly flat over a wide bandwidth (200MHz-1GHz), and an NF of approximately 4dB. The total power consumption is below 7.5 mW, with a very small die area of 0.007 mm2. All data are extracted from post-layout simulations.

Original language	English
Title of host publication	Proceedings 28. Norchip Conference
Place of Publication	Tampere, Finland
Publication date	2010
Publication status	Published - 2010
Event	28th Norchip Conference - Tampere, Finland Duration: 15 Nov 2010 → 16 Nov 2010

Conference

Conference	28th Norchip Conference
Country	Finland
City	Tampere
Period	15/11/2010 → 16/11/2010

Keywords

Inverter based amplifiers
Area
Noise canceling
CMOS
Wideband Balun LNA
LNAs
Self-Biased

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Cite this

@inproceedings{5f9c828e08dc447aab47ff4e210e0275,

title = "A Small-Area Self-Biased Wideband CMOS Balun LNA with Noise Cancelling and Gain Enhancement",

abstract = "In this paper we present a low-power and small-area balun LNA. The proposed inverter-based topology uses selfbiasing and noise cancelling, yielding a very robust LNA with a low NF. Comparing this circuit with a conventional inverterbased circuit, we obtain a ∼3 dB enhancement in voltage gain, with improved robustness against PVT variations. Simulations results in a 130 nm CMOS technology show a 17.7dB voltage gain, nearly flat over a wide bandwidth (200MHz-1GHz), and an NF of approximately 4dB. The total power consumption is below 7.5 mW, with a very small die area of 0.007 mm2. All data are extracted from post-layout simulations.",

keywords = "Inverter based amplifiers, Area, Noise canceling, CMOS, Wideband Balun LNA, LNAs, Self-Biased",

author = "Erik Bruun and Pietro Andreani and Cust{\'o}dio, {J. R.} and J. Goes and Oliveira, {J. P.} and Oliveira, {L. B.}",

year = "2010",

language = "English",

booktitle = "Proceedings 28. Norchip Conference",

note = "28th Norchip Conference ; Conference date: 15-11-2010 Through 16-11-2010",

}

TY - GEN

T1 - A Small-Area Self-Biased Wideband CMOS Balun LNA with Noise Cancelling and Gain Enhancement

AU - Bruun, Erik

AU - Andreani, Pietro

AU - Custódio, J. R.

AU - Goes, J.

AU - Oliveira, J. P.

AU - Oliveira, L. B.

PY - 2010

Y1 - 2010

N2 - In this paper we present a low-power and small-area balun LNA. The proposed inverter-based topology uses selfbiasing and noise cancelling, yielding a very robust LNA with a low NF. Comparing this circuit with a conventional inverterbased circuit, we obtain a ∼3 dB enhancement in voltage gain, with improved robustness against PVT variations. Simulations results in a 130 nm CMOS technology show a 17.7dB voltage gain, nearly flat over a wide bandwidth (200MHz-1GHz), and an NF of approximately 4dB. The total power consumption is below 7.5 mW, with a very small die area of 0.007 mm2. All data are extracted from post-layout simulations.

AB - In this paper we present a low-power and small-area balun LNA. The proposed inverter-based topology uses selfbiasing and noise cancelling, yielding a very robust LNA with a low NF. Comparing this circuit with a conventional inverterbased circuit, we obtain a ∼3 dB enhancement in voltage gain, with improved robustness against PVT variations. Simulations results in a 130 nm CMOS technology show a 17.7dB voltage gain, nearly flat over a wide bandwidth (200MHz-1GHz), and an NF of approximately 4dB. The total power consumption is below 7.5 mW, with a very small die area of 0.007 mm2. All data are extracted from post-layout simulations.

KW - Inverter based amplifiers

KW - Area

KW - Noise canceling

KW - CMOS

KW - Wideband Balun LNA

KW - LNAs

KW - Self-Biased

M3 - Article in proceedings

BT - Proceedings 28. Norchip Conference

CY - Tampere, Finland

T2 - 28th Norchip Conference

Y2 - 15 November 2010 through 16 November 2010

ER -