TY - JOUR
T1 - A Single-Phase Reduced Component Count Asymmetrical Multilevel Inverter Topology
AU - Yeganeh, Mohammad Sadegh Orfi
AU - Davari, Pooya
AU - Chub, Andrii
AU - Mijatovic, Nenad
AU - Dragicevic, Tomislav
AU - Blaabjerg, Frede
PY - 2021
Y1 - 2021
N2 - Multilevel inverters (MLIs) have gained wide attention in industry and academia to provide higher voltage levels with lower harmonics, power losses, and cost. This study proposes a new asymmetrical MLI topology with reduced component count (RCC). The proposed topology can be extended in a three-phase structure and both modular and cascaded configurations to generate the required number of voltage levels for high-voltage applications. To minimize the power losses and the voltage stress on the switches, this configuration has the potential to produce negative polarity without an H-bridge configuration, thereby the active switches are reduced to only three switches in the conduction path. Due to the possibility of applying different switching patterns, this paper proposes a new solution by employing particle swarm optimization (PSO) algorithm to determine the optimized DC sources’ magnitude. To improve the voltage quality and minimize the total harmonic distortion (THD), the optimal switching angle (OSA) modulation technique is applied to determine the optimum switching angles by PSO algorithm. Moreover, the proposed topology’s effectiveness compared to the conventional cascaded H-bridge (CHB) MLI with 15-levels is illustrated by providing comparative results that express fewer power losses. Finally, the proposed topology’s feasibility and its optimization approach are validated by a single-phase prototype utilizing 15- and 25-levels.
AB - Multilevel inverters (MLIs) have gained wide attention in industry and academia to provide higher voltage levels with lower harmonics, power losses, and cost. This study proposes a new asymmetrical MLI topology with reduced component count (RCC). The proposed topology can be extended in a three-phase structure and both modular and cascaded configurations to generate the required number of voltage levels for high-voltage applications. To minimize the power losses and the voltage stress on the switches, this configuration has the potential to produce negative polarity without an H-bridge configuration, thereby the active switches are reduced to only three switches in the conduction path. Due to the possibility of applying different switching patterns, this paper proposes a new solution by employing particle swarm optimization (PSO) algorithm to determine the optimized DC sources’ magnitude. To improve the voltage quality and minimize the total harmonic distortion (THD), the optimal switching angle (OSA) modulation technique is applied to determine the optimum switching angles by PSO algorithm. Moreover, the proposed topology’s effectiveness compared to the conventional cascaded H-bridge (CHB) MLI with 15-levels is illustrated by providing comparative results that express fewer power losses. Finally, the proposed topology’s feasibility and its optimization approach are validated by a single-phase prototype utilizing 15- and 25-levels.
U2 - 10.1109/JESTPE.2021.3066396
DO - 10.1109/JESTPE.2021.3066396
M3 - Journal article
SN - 2168-6777
VL - 9
SP - 6780
EP - 6790
JO - IEEE Journal of Emerging and Selected Topics in Power Electronics
JF - IEEE Journal of Emerging and Selected Topics in Power Electronics
IS - 6
ER -