A Single-Path Chip-Multiprocessor System

Martin Schoeberl; Peter Puschner; Raimund Kirner

A Single-Path Chip-Multiprocessor System

Martin Schoeberl, Peter Puschner, Raimund Kirner

TU Wien

Research output: Chapter in Book/Report/Conference proceeding › Article in proceedings › Research › peer-review

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Abstract

. In this paper we explore the combination of a time-predictable chipmultiprocessor system with the single-path programming paradigm. Time-sliced arbitration of the main memory access provides time-predictable memory load and store instructions. Single-path programming avoids control flow dependent timing variations. To keep the execution time of tasks constant, even in the case of shared memory access of several processor cores, the tasks on the cores are synchronized with the time-sliced memory arbitration unit.

Original language	English
Title of host publication	Proceedings of the Seventh IFIP Workshop on Software Technologies for Future Embedded and Ubiquitous Systems (SEUS 2009)
Publication date	2009
Pages	47-57
Publication status	Published - 2009
Externally published	Yes
Event	Seventh IFIP Workshop on Software Technologies for Future Embedded and Ubiquitous Systems (SEUS 2009) - Newport Beach, (CA), United States Duration: 16 Nov 2009 → 18 Nov 2009 Conference number: 7

Conference

Conference	Seventh IFIP Workshop on Software Technologies for Future Embedded and Ubiquitous Systems (SEUS 2009)
Number	7
Country/Territory	United States
City	Newport Beach, (CA)
Period	16/11/2009 → 18/11/2009

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title = "A Single-Path Chip-Multiprocessor System",

abstract = ". In this paper we explore the combination of a time-predictable chipmultiprocessor system with the single-path programming paradigm. Time-sliced arbitration of the main memory access provides time-predictable memory load and store instructions. Single-path programming avoids control flow dependent timing variations. To keep the execution time of tasks constant, even in the case of shared memory access of several processor cores, the tasks on the cores are synchronized with the time-sliced memory arbitration unit. ",

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year = "2009",

language = "English",

pages = "47--57",

booktitle = "Proceedings of the Seventh IFIP Workshop on Software Technologies for Future Embedded and Ubiquitous Systems (SEUS 2009)",

note = "Seventh IFIP Workshop on Software Technologies for Future Embedded and Ubiquitous Systems (SEUS 2009), SEUS 2009 ; Conference date: 16-11-2009 Through 18-11-2009",

}

Schoeberl, M, Puschner, P & Kirner, R 2009, A Single-Path Chip-Multiprocessor System. in Proceedings of the Seventh IFIP Workshop on Software Technologies for Future Embedded and Ubiquitous Systems (SEUS 2009). pp. 47-57, Seventh IFIP Workshop on Software Technologies for Future Embedded and Ubiquitous Systems (SEUS 2009), Newport Beach, (CA), United States, 16/11/2009.

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AU - Schoeberl, Martin

AU - Puschner, Peter

AU - Kirner, Raimund

N1 - Conference code: 7

PY - 2009

Y1 - 2009

N2 - . In this paper we explore the combination of a time-predictable chipmultiprocessor system with the single-path programming paradigm. Time-sliced arbitration of the main memory access provides time-predictable memory load and store instructions. Single-path programming avoids control flow dependent timing variations. To keep the execution time of tasks constant, even in the case of shared memory access of several processor cores, the tasks on the cores are synchronized with the time-sliced memory arbitration unit.

AB - . In this paper we explore the combination of a time-predictable chipmultiprocessor system with the single-path programming paradigm. Time-sliced arbitration of the main memory access provides time-predictable memory load and store instructions. Single-path programming avoids control flow dependent timing variations. To keep the execution time of tasks constant, even in the case of shared memory access of several processor cores, the tasks on the cores are synchronized with the time-sliced memory arbitration unit.

M3 - Article in proceedings

SP - 47

EP - 57

BT - Proceedings of the Seventh IFIP Workshop on Software Technologies for Future Embedded and Ubiquitous Systems (SEUS 2009)

T2 - Seventh IFIP Workshop on Software Technologies for Future Embedded and Ubiquitous Systems (SEUS 2009)

Y2 - 16 November 2009 through 18 November 2009

ER -

A Single-Path Chip-Multiprocessor System

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