A Short Term Analogue Memory

Peter Jivan Shah

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    Abstract

    A short term analogue memory is described. It is based on a well-known sample-hold topology in which leakage currents have been minimized partly by circuit design and partly by layout techniques. Measurements on a test chip implemented in a standard 2.4 micron analogue CMOS process show a droop rate of 0.075mV per second with a 1pF hold capacitor. This is equivalent to a retention time of approximately 1½ minute with 10 bits accuracy, assuming a full scale of +/-3.5V. It is expected that this can be improved by more than an order of magnitude by improving the layout of the hold capacitor. Thus hold times of several hours should be achievable with moderate capacitance values.
    Original languageEnglish
    Title of host publicationProceedings of the 18th European Solid-State Circuits Conference
    PublisherIEEE
    Publication date1992
    Pages127-130
    ISBN (Print)87-98-42320-7
    Publication statusPublished - 1992
    Event18th European Solid-State Circuits Conference - Copenhagen, Denmark
    Duration: 21 Sep 199223 Sep 1992
    Conference number: 18
    http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=5468103

    Conference

    Conference18th European Solid-State Circuits Conference
    Number18
    Country/TerritoryDenmark
    CityCopenhagen
    Period21/09/199223/09/1992
    Internet address

    Bibliographical note

    Copyright 1992 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.

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