A Short Term Analogue Memory

Peter Jivan Shah

A Short Term Analogue Memory

Peter Jivan Shah

Research output: Chapter in Book/Report/Conference proceeding › Article in proceedings › Research › peer-review

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Abstract

A short term analogue memory is described. It is based on a well-known sample-hold topology in which leakage currents have been minimized partly by circuit design and partly by layout techniques. Measurements on a test chip implemented in a standard 2.4 micron analogue CMOS process show a droop rate of 0.075mV per second with a 1pF hold capacitor. This is equivalent to a retention time of approximately 1Â½ minute with 10 bits accuracy, assuming a full scale of +/-3.5V. It is expected that this can be improved by more than an order of magnitude by improving the layout of the hold capacitor. Thus hold times of several hours should be achievable with moderate capacitance values.

Original language	English
Title of host publication	Proceedings of the 18th European Solid-State Circuits Conference
Publisher	IEEE
Publication date	1992
Pages	127-130
ISBN (Print)	87-98-42320-7
Publication status	Published - 1992
Event	18th European Solid-State Circuits Conference - Copenhagen, Denmark Duration: 21 Sept 1992 → 23 Sept 1992 Conference number: 18 http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=5468103

Conference

Conference	18th European Solid-State Circuits Conference
Number	18
Country/Territory	Denmark
City	Copenhagen
Period	21/09/1992 → 23/09/1992
Internet address	http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=5468103

Bibliographical note

Copyright 1992 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.

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@inproceedings{05faa79faa434a5291eb89114694e81d,

title = "A Short Term Analogue Memory",

abstract = "A short term analogue memory is described. It is based on a well-known sample-hold topology in which leakage currents have been minimized partly by circuit design and partly by layout techniques. Measurements on a test chip implemented in a standard 2.4 micron analogue CMOS process show a droop rate of 0.075mV per second with a 1pF hold capacitor. This is equivalent to a retention time of approximately 1{\^A}½ minute with 10 bits accuracy, assuming a full scale of +/-3.5V. It is expected that this can be improved by more than an order of magnitude by improving the layout of the hold capacitor. Thus hold times of several hours should be achievable with moderate capacitance values.",

author = "Shah, {Peter Jivan}",

note = "Copyright 1992 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.; 18th European Solid-State Circuits Conference, ESSCIRC '92 ; Conference date: 21-09-1992 Through 23-09-1992",

year = "1992",

language = "English",

isbn = "87-98-42320-7",

pages = "127--130",

booktitle = "Proceedings of the 18th European Solid-State Circuits Conference",

publisher = "IEEE",

address = "United States",

url = "http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=5468103",

}

TY - GEN

T1 - A Short Term Analogue Memory

AU - Shah, Peter Jivan

N1 - Conference code: 18

PY - 1992

Y1 - 1992

N2 - A short term analogue memory is described. It is based on a well-known sample-hold topology in which leakage currents have been minimized partly by circuit design and partly by layout techniques. Measurements on a test chip implemented in a standard 2.4 micron analogue CMOS process show a droop rate of 0.075mV per second with a 1pF hold capacitor. This is equivalent to a retention time of approximately 1Â½ minute with 10 bits accuracy, assuming a full scale of +/-3.5V. It is expected that this can be improved by more than an order of magnitude by improving the layout of the hold capacitor. Thus hold times of several hours should be achievable with moderate capacitance values.

AB - A short term analogue memory is described. It is based on a well-known sample-hold topology in which leakage currents have been minimized partly by circuit design and partly by layout techniques. Measurements on a test chip implemented in a standard 2.4 micron analogue CMOS process show a droop rate of 0.075mV per second with a 1pF hold capacitor. This is equivalent to a retention time of approximately 1Â½ minute with 10 bits accuracy, assuming a full scale of +/-3.5V. It is expected that this can be improved by more than an order of magnitude by improving the layout of the hold capacitor. Thus hold times of several hours should be achievable with moderate capacitance values.

M3 - Article in proceedings

SN - 87-98-42320-7

SP - 127

EP - 130

BT - Proceedings of the 18th European Solid-State Circuits Conference

PB - IEEE

T2 - 18th European Solid-State Circuits Conference

Y2 - 21 September 1992 through 23 September 1992

ER -

A Short Term Analogue Memory

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