A Shared Scratchpad Memory with Synchronization Support

Henrik Enggaard Hansen, Emad Jacob Maroun, Andreas Toftegaard Kristensen, Martin Schoeberl, Jimmi Marquart

Research output: Chapter in Book/Report/Conference proceedingArticle in proceedingsResearchpeer-review

400 Downloads (Pure)


Multicore processors usually communicate via shared memory, which is backed up by a shared level 2 cache and a cache coherence protocol. However, this solution is not a good fit for real-time systems, where we need to provide tight guarantees on execution and memory access times. In this paper, we propose a shared scratchpad memory as a time-predictable communication and synchronization structure, instead of the level 2 cache. The shared on-chip memory is accessed via a time division multiplexing arbiter, isolating the execution time of load and store instructions between processing cores. Furthermore, the arbiter supports an extended time slot where an atomic load and store instruction can be executed to implement synchronization primitives. In the evaluation we show that a shared scratchpad memory is an efficient communication structure for a small number of processors; in our setup, 9 cores. Furthermore, we evaluate the efficiency of the synchronization support for implementation of classic locks.
Original languageEnglish
Title of host publicationProceedings of the IEEE NorCAS 2017
Number of pages6
Publication date2017
ISBN (Print)978-1-5386-2844-7
Publication statusPublished - 2017
EventNordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC) - Linköping Konsert & Kongress, Linköping, Sweden
Duration: 23 Oct 201725 Oct 2017


ConferenceNordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)
LocationLinköping Konsert & Kongress
Internet address


Dive into the research topics of 'A Shared Scratchpad Memory with Synchronization Support'. Together they form a unique fingerprint.

Cite this