A Scalable, Timing-Safe, Network-on-Chip Architecture with an Integrated Clock Distribution Method

Tobias Bjerregaard; Mikkel Bystrup Stensgaard; Jens Sparsø

doi:10.1109/DATE.2007.364667

A Scalable, Timing-Safe, Network-on-Chip Architecture with an Integrated Clock Distribution Method

Tobias Bjerregaard, Mikkel Bystrup Stensgaard, Jens Sparsø

Research output: Chapter in Book/Report/Conference proceeding › Article in proceedings › Research › peer-review

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Abstract

Growing system sizes together with increasing performance variability are making globally synchronous operation hard to realize. Mesochronous clocking constitutes a possible solution to the problems faced. The most fundamental of problems faced when communicating between mesochronously clocked regions concerns the possibility of data corruption caused by metastability. This paper presents an integrated communication and mesochronous clocking strategy, which avoids timing related errors while maintaining a globally synchronous system perspective. The architecture is scalable as timing integrity is based purely on local observations. It is demonstrated with a 90 nm CMOS standard cell network-on-chip design which implements completely timing-safe, global communication in a modular system

Original language	English
Title of host publication	Design, Automation & Test in Europe Conference & Exhibition, 2007. DATE '07
Publisher	IEEE
Publication date	2007
Pages	1-6
ISBN (Print)	978-3-9810801-2-4
DOIs	https://doi.org/10.1109/DATE.2007.364667
Publication status	Published - 2007
Event	2007 Design, Automation and Test in Europe Conference and Exposition - Nice, France Duration: 16 Apr 2007 → 20 Apr 2007 http://www.informatik.uni-trier.de/~ley/db/conf/date/date2007.html

Conference

Conference	2007 Design, Automation and Test in Europe Conference and Exposition
Country/Territory	France
City	Nice
Period	16/04/2007 → 20/04/2007
Internet address	http://www.informatik.uni-trier.de/~ley/db/conf/date/date2007.html

Bibliographical note

Copyright: 2007 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE

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@inproceedings{7c6a8044b5734aa896679bcd2949b415,

title = "A Scalable, Timing-Safe, Network-on-Chip Architecture with an Integrated Clock Distribution Method",

abstract = "Growing system sizes together with increasing performance variability are making globally synchronous operation hard to realize. Mesochronous clocking constitutes a possible solution to the problems faced. The most fundamental of problems faced when communicating between mesochronously clocked regions concerns the possibility of data corruption caused by metastability. This paper presents an integrated communication and mesochronous clocking strategy, which avoids timing related errors while maintaining a globally synchronous system perspective. The architecture is scalable as timing integrity is based purely on local observations. It is demonstrated with a 90 nm CMOS standard cell network-on-chip design which implements completely timing-safe, global communication in a modular system",

author = "Tobias Bjerregaard and Stensgaard, {Mikkel Bystrup} and Jens Spars{\o}",

note = "Copyright: 2007 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE; 2007 Design, Automation and Test in Europe Conference and Exposition, DATE 2007 ; Conference date: 16-04-2007 Through 20-04-2007",

year = "2007",

doi = "10.1109/DATE.2007.364667",

language = "English",

isbn = "978-3-9810801-2-4",

pages = "1--6",

booktitle = "Design, Automation & Test in Europe Conference & Exhibition, 2007. DATE '07",

publisher = "IEEE",

address = "United States",

url = "http://www.informatik.uni-trier.de/~ley/db/conf/date/date2007.html",

}

Bjerregaard, T, Stensgaard, MB & Sparsø, J 2007, A Scalable, Timing-Safe, Network-on-Chip Architecture with an Integrated Clock Distribution Method. in Design, Automation & Test in Europe Conference & Exhibition, 2007. DATE '07. IEEE, pp. 1-6, 2007 Design, Automation and Test in Europe Conference and Exposition, Nice, France, 16/04/2007. https://doi.org/10.1109/DATE.2007.364667

A Scalable, Timing-Safe, Network-on-Chip Architecture with an Integrated Clock Distribution Method. / Bjerregaard, Tobias; Stensgaard, Mikkel Bystrup; Sparsø, Jens.
Design, Automation & Test in Europe Conference & Exhibition, 2007. DATE '07. IEEE, 2007. p. 1-6.

Research output: Chapter in Book/Report/Conference proceeding › Article in proceedings › Research › peer-review

TY - GEN

T1 - A Scalable, Timing-Safe, Network-on-Chip Architecture with an Integrated Clock Distribution Method

AU - Bjerregaard, Tobias

AU - Stensgaard, Mikkel Bystrup

AU - Sparsø, Jens

N1 - Copyright: 2007 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE

PY - 2007

Y1 - 2007

N2 - Growing system sizes together with increasing performance variability are making globally synchronous operation hard to realize. Mesochronous clocking constitutes a possible solution to the problems faced. The most fundamental of problems faced when communicating between mesochronously clocked regions concerns the possibility of data corruption caused by metastability. This paper presents an integrated communication and mesochronous clocking strategy, which avoids timing related errors while maintaining a globally synchronous system perspective. The architecture is scalable as timing integrity is based purely on local observations. It is demonstrated with a 90 nm CMOS standard cell network-on-chip design which implements completely timing-safe, global communication in a modular system

AB - Growing system sizes together with increasing performance variability are making globally synchronous operation hard to realize. Mesochronous clocking constitutes a possible solution to the problems faced. The most fundamental of problems faced when communicating between mesochronously clocked regions concerns the possibility of data corruption caused by metastability. This paper presents an integrated communication and mesochronous clocking strategy, which avoids timing related errors while maintaining a globally synchronous system perspective. The architecture is scalable as timing integrity is based purely on local observations. It is demonstrated with a 90 nm CMOS standard cell network-on-chip design which implements completely timing-safe, global communication in a modular system

U2 - 10.1109/DATE.2007.364667

DO - 10.1109/DATE.2007.364667

M3 - Article in proceedings

SN - 978-3-9810801-2-4

SP - 1

EP - 6

BT - Design, Automation & Test in Europe Conference & Exhibition, 2007. DATE '07

PB - IEEE

T2 - 2007 Design, Automation and Test in Europe Conference and Exposition

Y2 - 16 April 2007 through 20 April 2007

ER -

A Scalable, Timing-Safe, Network-on-Chip Architecture with an Integrated Clock Distribution Method

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