Abstract
On-chip networks for future system-on-chip designs need simple, high performance implementations. In order to promote system-level integrity, guaranteed services (GS) need to be provided. We propose a network-on-chip (NoC) router architecture to support this, and demonstrate with a CMOS standard cell design. Our implementation is based on clockless circuit techniques, and thus inherently supports a modular, GALS-oriented design flow. Our router exploits virtual channels to provide connection-oriented GS, as well as connection-less best-effort (BE) routing. The architecture is highly flexible, in that support for different types of BE routing and GS arbitration can be easily plugged into the router.
Original language | English |
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Title of host publication | Proceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE’05) |
Place of Publication | IEEE |
Publisher | IEEE Computer Society Press |
Publication date | 2005 |
Pages | 1226-1231 |
ISBN (Print) | 0-7695-2288-2 |
DOIs | |
Publication status | Published - 2005 |
Event | 2005 Design, Automation and Test in Europe Conference and Exposition - Munich, Germany Duration: 7 Mar 2005 → 11 Mar 2005 http://www.informatik.uni-trier.de/~ley/db/conf/date/date2005.html |
Conference
Conference | 2005 Design, Automation and Test in Europe Conference and Exposition |
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Country/Territory | Germany |
City | Munich |
Period | 07/03/2005 → 11/03/2005 |
Internet address |
Bibliographical note
Copyright: 2005 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEEKeywords
- asynchronous
- guaranteed services
- clockless
- Network-on-chip