A resource-efficient network interface supporting low latency reconfiguration of virtual circuits in time-division multiplexing networks-on-chip

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This paper presents a resource-efficient time-division multiplexing network interface of a network-on- chip intended for use in a multicore platform for hard real-time systems. The network-on-chip pro- vides virtual circuits to move data between core-local on-chip memories. In such a platform, a change of the application’s operating mode may require reconfiguration of virtual circuits that are setup by the network-on-chip. A unique feature of our network interface is the instantaneous reconfiguration between different time-division multiplexing schedules, containing sets of virtual circuits, without affecting virtual circuits that persist across the reconfiguration. The results show that the worst-case latency from trigger- ing a reconfiguration until the new schedule is executing, is in the range of 300 clock cycles. Experiments show that new schedules can be transmitted from a single master to all slave nodes for a 16-core plat- form in between 500 and 3500 clock cycles. The results also show that the hardware cost for an FPGA implementation of our architecture is considerably smaller than other network-on-chips with similar re- configuration functionalities, and that the worst-case time for a reconfiguration is smaller than that seen in functionally equivalent architectures.
Original languageEnglish
JournalJournal of Systems Architecture
Pages (from-to)1–13
Publication statusPublished - 2017


  • Network-on-chip
  • Real-time systems
  • Reconfiguration
  • Time-division multiplexing

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