A Reactive and Cycle-True IP Emulator for MPSoC Exploration

Shankar Mahadevan, Federico Angiolini, Jens Sparsø, Luca Benini, Jan Madsen

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    Abstract

    The design of MultiProcessor Systems-on-Chip (MPSoC) emphasizes intellectual-property (IP)-based communication-centric approaches. Therefore, for the optimization of the MPSoC interconnect, the designer must develop traffic models that realistically capture the application behavior as executing on the IP core. In this paper, we introduce a Reactive IP Emulator (RIPE) that enables an effective emulation of the IP-core behavior in multiple environments, including bit and cycle-true simulation. The RIPE is built as a multithreaded abstract instruction-set processor, and it can generate reactive traffic patterns. We compare the RIPE models with cycle-true functional simulation of complex application behavior (tasksynchronization, multitasking, and input/output operations). Our results demonstrate high-accuracy and significant speedups. Furthermore, via a case study, we show the potential use of the RIPE in a design-space-exploration context.
    Original languageEnglish
    JournalI E E E Transactions on Computer - Aided Design of Integrated Circuits and Systems
    Volume27
    Issue number1
    Pages (from-to)109-122
    ISSN0278-0070
    DOIs
    Publication statusPublished - 2008

    Bibliographical note

    Copyright: 2008 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE

    Keywords

    • Network traffic reproduction
    • Traffic profiling and trace parsing
    • Simulation
    • Traffic generator
    • Bus traffic modelling
    • Traffic shaping
    • Systems-on-chip
    • Cycle-true traffic generator
    • Reactive application models
    • Multi Processor Systems-on-Chip (MPSoC)
    • Simple instruction set architecture
    • Macromodelling
    • Multi-processing
    • Network-on-chip

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