A Radix-10 Combinational Multiplier

Tomas Lang; Alberto Nannarelli

doi:10.1109/ACSSC.2006.354758

A Radix-10 Combinational Multiplier

Tomas Lang
, Alberto Nannarelli

Research output: Chapter in Book/Report/Conference proceeding › Article in proceedings › Research › peer-review

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Abstract

In this work, we present a combinational decimal multiply unit which can be pipelined to reach the desired throughput. With respect to previous implementations of decimal multiplication, the proposed unit is combinational (parallel) and not sequential, has a simpler recoding of the operands which reduces the number of partial product precomputations and uses counters to eliminate the need of the decimal equivalent of a 4:2 adder. The results of the implementation show that the combinational decimal multiplier offers a good compromise between latency and area when compared to other decimal multiply units and to binary double-precision multipliers.

Original language	English
Title of host publication	Proceedings of 40th Asilomar Conference on Signals, Systems, and Computers
Publisher	IEEE
Publication date	2006
Pages	313-317
ISBN (Print)	1-4244-0784-2
DOIs	https://doi.org/10.1109/ACSSC.2006.354758
Publication status	Published - 2006
Event	40th Asilomar Conference on Signals, Systems, and Computers - Pacific Grove, CA, United States Duration: 29 Oct 2006 → 1 Nov 2006 Conference number: 40

Conference

Conference	40th Asilomar Conference on Signals, Systems, and Computers
Number	40
Country/Territory	United States
City	Pacific Grove, CA
Period	29/10/2006 → 01/11/2006

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@inproceedings{351dac15a4cc417593cd12df9c7fc8c8,

title = "A Radix-10 Combinational Multiplier",

abstract = "In this work, we present a combinational decimal multiply unit which can be pipelined to reach the desired throughput. With respect to previous implementations of decimal multiplication, the proposed unit is combinational (parallel) and not sequential, has a simpler recoding of the operands which reduces the number of partial product precomputations and uses counters to eliminate the need of the decimal equivalent of a 4:2 adder. The results of the implementation show that the combinational decimal multiplier offers a good compromise between latency and area when compared to other decimal multiply units and to binary double-precision multipliers.",

author = "Tomas Lang and Alberto Nannarelli",

year = "2006",

doi = "10.1109/ACSSC.2006.354758",

language = "English",

isbn = "1-4244-0784-2",

pages = "313--317",

booktitle = "Proceedings of 40th Asilomar Conference on Signals, Systems, and Computers",

publisher = "IEEE",

address = "United States",

note = "40th Asilomar Conference on Signals, Systems, and Computers ; Conference date: 29-10-2006 Through 01-11-2006",

}

TY - GEN

T1 - A Radix-10 Combinational Multiplier

AU - Lang, Tomas

AU - Nannarelli, Alberto

N1 - Conference code: 40

PY - 2006

Y1 - 2006

N2 - In this work, we present a combinational decimal multiply unit which can be pipelined to reach the desired throughput. With respect to previous implementations of decimal multiplication, the proposed unit is combinational (parallel) and not sequential, has a simpler recoding of the operands which reduces the number of partial product precomputations and uses counters to eliminate the need of the decimal equivalent of a 4:2 adder. The results of the implementation show that the combinational decimal multiplier offers a good compromise between latency and area when compared to other decimal multiply units and to binary double-precision multipliers.

AB - In this work, we present a combinational decimal multiply unit which can be pipelined to reach the desired throughput. With respect to previous implementations of decimal multiplication, the proposed unit is combinational (parallel) and not sequential, has a simpler recoding of the operands which reduces the number of partial product precomputations and uses counters to eliminate the need of the decimal equivalent of a 4:2 adder. The results of the implementation show that the combinational decimal multiplier offers a good compromise between latency and area when compared to other decimal multiply units and to binary double-precision multipliers.

U2 - 10.1109/ACSSC.2006.354758

DO - 10.1109/ACSSC.2006.354758

M3 - Article in proceedings

SN - 1-4244-0784-2

SP - 313

EP - 317

BT - Proceedings of 40th Asilomar Conference on Signals, Systems, and Computers

PB - IEEE

T2 - 40th Asilomar Conference on Signals, Systems, and Computers

Y2 - 29 October 2006 through 1 November 2006

ER -

A Radix-10 Combinational Multiplier

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