In this work, we present a combinational decimal multiply unit which can be pipelined to reach the desired throughput. With respect to previous implementations of decimal multiplication, the proposed unit is combinational (parallel) and not sequential, has a simpler recoding of the operands which reduces the number of partial product precomputations and uses counters to eliminate the need of the decimal equivalent of a 4:2 adder. The results of the implementation show that the combinational decimal multiplier offers a good compromise between latency and area when compared to other decimal multiply units and to binary double-precision multipliers.
|Title of host publication||Proceedings of 40th Asilomar Conference on Signals, Systems, and Computers|
|Publication status||Published - 2006|
|Event||Asilomar Conference on Signals, Systems, and Computers - |
Duration: 1 Jan 2006 → …
Conference number: 40
|Conference||Asilomar Conference on Signals, Systems, and Computers|
|Period||01/01/2006 → …|