Abstract
In this work, we present a combinational decimal
multiply unit which can be pipelined to reach the desired
throughput. With respect to previous implementations of decimal
multiplication, the proposed unit is combinational (parallel) and
not sequential, has a simpler recoding of the operands which
reduces the number of partial product precomputations and
uses counters to eliminate the need of the decimal equivalent
of a 4:2 adder. The results of the implementation show that
the combinational decimal multiplier offers a good compromise
between latency and area when compared to other decimal
multiply units and to binary double-precision multipliers.
Original language | English |
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Title of host publication | Proceedings of 40th Asilomar Conference on Signals, Systems, and Computers |
Publisher | IEEE |
Publication date | 2006 |
Pages | 313-317 |
ISBN (Print) | 1-4244-0784-2 |
DOIs | |
Publication status | Published - 2006 |
Event | Asilomar Conference on Signals, Systems, and Computers - Duration: 1 Jan 2006 → … Conference number: 40 |
Conference
Conference | Asilomar Conference on Signals, Systems, and Computers |
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Number | 40 |
Period | 01/01/2006 → … |