A Nordic Project Project on High Speed Low Power Design in Sub-micron CMOS Technology for Mobile

This paper is a survey paper presenting the Nordic CONFRONT project and reporting some results from the group at CIE/DTU, Denmark. The objective of the project is to demonstrate the feasibility of sub-micron CMOS for the realisation of RF front-end circuits operating at frequencies in the 1.8-2.0 GHz range. The ultimate goal is a single-chip transceiver, requiring only an external band-pass filter between the chip and the antenna. DECT has been chosen as a comparative standard to compare the new approaches developed in the work as well as to facilitate good knowledge transfer to industry. All circuit design is based on state-of-the-art CMOS technology (0.5µm and below) including circuits operating at 2GHz. CMOS technology is chosen, since a CMOS implementation is likely to be significantly cheaper than a bipolar or a BiCMOS solution, and it offers the possibility to integrate the predominantly digital base-band processing on the same chip. Presently, only few examples of CMOS used for RF front-end circuits have been presented by academia, and so far no commercial products exist. The approach has been to do a CMOS block by block replacement of the blocks in traditional transceiver architectures. We feel that this approach is not ideal, since the excellent sampling properties of CMOS are not utilised. Therefore, the work focuses on developing transceiver architectures and circuits that truly exploit the desirable properties. At the same time, the work will investigate the possibility of including good off-chip components in the design by use of innovative, inexpensive package technology.To achieve a higher level of integration, the project will use a novel codesign approach to the design strategy. Rather than making specifications based on a purely architectural approach, the work uses a concurrent approach, where circuit designers and architecture designers co-operate on the design and specifications. This allows more circuit issues to be included in the overall architecture, hopefully resulting in an architecture with circuit blocks suited for full integration.