A set of algorithms is presented for optimal layout generation of CMOS complex gates. The algorithms are able to handle global physical constraints, such as pin placement, and to capture timing aspects. Results show that this novel approach provides better solutions in area and speed compared t other methods. The algorithms have been implemented in a cell compiler (CELLO) working in an experimental silicon compiler environment.
|Title of host publication||Proceedings of the IEEE International Conference on Computer-Aided Design, ICCAD-89|
|Publication status||Published - 1989|
|Event||International Conference on Computer-Aided Design - Santa Clara, CA|
Duration: 1 Jan 1989 → …
|Conference||International Conference on Computer-Aided Design|
|City||Santa Clara, CA|
|Period||01/01/1989 → …|