A Neuron- and a Synapse Chip for Artificial Neural Networks

John Lansner, Torsten Lehmann

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    Abstract

    A cascadable, analog, CMOS chip set has been developed for hardware implementations of artificial neural networks (ANN's):I) a neuron chip containing an array of neurons with hyperbolic tangent activation functions and adjustable gains, and II) a synapse chip (or a matrix-vector multiplier) where the matrix is stored on-chip as differential voltages on capacitors. In principal any ANN configuration can be made using these chips. A neuron array of 4 neurons and a 4 × 4 matrix-vector multiplier has been fabricated in a standard 2.4 ¿m CMOS process for test purposes. The propagation time through the synapse and neuron chips is less than 4 ¿s and the weight matrix has a 10 bit resolution.
    Original languageEnglish
    Title of host publicationProceedings of the 18th European Solid-State Circuits Conference
    PublisherIEEE
    Publication date1992
    Pages213-216
    ISBN (Print)87-98-42320-7
    Publication statusPublished - 1992
    Event18th European Solid-State Circuits Conference - Copenhagen, Denmark
    Duration: 21 Sep 199223 Sep 1992
    Conference number: 18
    http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=5468103

    Conference

    Conference18th European Solid-State Circuits Conference
    Number18
    CountryDenmark
    CityCopenhagen
    Period21/09/199223/09/1992
    Internet address

    Bibliographical note

    Copyright: 1992 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE

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