A Neuron- and a Synapse Chip for Artificial Neural Networks

John Lansner; Torsten Lehmann

A Neuron- and a Synapse Chip for Artificial Neural Networks

John Lansner, Torsten Lehmann

Research output: Chapter in Book/Report/Conference proceeding › Article in proceedings › Research › peer-review

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Abstract

A cascadable, analog, CMOS chip set has been developed for hardware implementations of artificial neural networks (ANN's):I) a neuron chip containing an array of neurons with hyperbolic tangent activation functions and adjustable gains, and II) a synapse chip (or a matrix-vector multiplier) where the matrix is stored on-chip as differential voltages on capacitors. In principal any ANN configuration can be made using these chips. A neuron array of 4 neurons and a 4 Ã— 4 matrix-vector multiplier has been fabricated in a standard 2.4 Â¿m CMOS process for test purposes. The propagation time through the synapse and neuron chips is less than 4 Â¿s and the weight matrix has a 10 bit resolution.

Original language	English
Title of host publication	Proceedings of the 18th European Solid-State Circuits Conference
Publisher	IEEE
Publication date	1992
Pages	213-216
ISBN (Print)	87-98-42320-7
Publication status	Published - 1992
Event	18th European Solid-State Circuits Conference - Copenhagen, Denmark Duration: 21 Sept 1992 → 23 Sept 1992 Conference number: 18 http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=5468103

Conference

Conference	18th European Solid-State Circuits Conference
Number	18
Country/Territory	Denmark
City	Copenhagen
Period	21/09/1992 → 23/09/1992
Internet address	http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=5468103

Bibliographical note

Copyright: 1992 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE

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title = "A Neuron- and a Synapse Chip for Artificial Neural Networks",

abstract = "A cascadable, analog, CMOS chip set has been developed for hardware implementations of artificial neural networks (ANN's):I) a neuron chip containing an array of neurons with hyperbolic tangent activation functions and adjustable gains, and II) a synapse chip (or a matrix-vector multiplier) where the matrix is stored on-chip as differential voltages on capacitors. In principal any ANN configuration can be made using these chips. A neuron array of 4 neurons and a 4 {\~A}— 4 matrix-vector multiplier has been fabricated in a standard 2.4 {\^A}¿m CMOS process for test purposes. The propagation time through the synapse and neuron chips is less than 4 {\^A}¿s and the weight matrix has a 10 bit resolution.",

author = "John Lansner and Torsten Lehmann",

note = "Copyright: 1992 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE; 18th European Solid-State Circuits Conference, ESSCIRC '92 ; Conference date: 21-09-1992 Through 23-09-1992",

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AU - Lehmann, Torsten

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N2 - A cascadable, analog, CMOS chip set has been developed for hardware implementations of artificial neural networks (ANN's):I) a neuron chip containing an array of neurons with hyperbolic tangent activation functions and adjustable gains, and II) a synapse chip (or a matrix-vector multiplier) where the matrix is stored on-chip as differential voltages on capacitors. In principal any ANN configuration can be made using these chips. A neuron array of 4 neurons and a 4 Ã— 4 matrix-vector multiplier has been fabricated in a standard 2.4 Â¿m CMOS process for test purposes. The propagation time through the synapse and neuron chips is less than 4 Â¿s and the weight matrix has a 10 bit resolution.

AB - A cascadable, analog, CMOS chip set has been developed for hardware implementations of artificial neural networks (ANN's):I) a neuron chip containing an array of neurons with hyperbolic tangent activation functions and adjustable gains, and II) a synapse chip (or a matrix-vector multiplier) where the matrix is stored on-chip as differential voltages on capacitors. In principal any ANN configuration can be made using these chips. A neuron array of 4 neurons and a 4 Ã— 4 matrix-vector multiplier has been fabricated in a standard 2.4 Â¿m CMOS process for test purposes. The propagation time through the synapse and neuron chips is less than 4 Â¿s and the weight matrix has a 10 bit resolution.

M3 - Article in proceedings

SN - 87-98-42320-7

SP - 213

EP - 216

BT - Proceedings of the 18th European Solid-State Circuits Conference

PB - IEEE

T2 - 18th European Solid-State Circuits Conference

Y2 - 21 September 1992 through 23 September 1992

ER -

A Neuron- and a Synapse Chip for Artificial Neural Networks

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