A cascadable, analog, CMOS chip set has been developed for hardware implementations of artificial neural networks (ANN's):I) a neuron chip containing an array of neurons with hyperbolic tangent activation functions and adjustable gains, and II) a synapse chip (or a matrix-vector multiplier) where the matrix is stored on-chip as differential voltages on capacitors. In principal any ANN configuration can be made using these chips. A neuron array of 4 neurons and a 4 Ã— 4 matrix-vector multiplier has been fabricated in a standard 2.4 Â¿m CMOS process for test purposes. The propagation time through the synapse and neuron chips is less than 4 Â¿s and the weight matrix has a 10 bit resolution.
|Title of host publication||Proceedings of the 18th European Solid-State Circuits Conference|
|Publication status||Published - 1992|
|Event||18th European Solid-State Circuits Conference - Copenhagen, Denmark|
Duration: 21 Sep 1992 → 23 Sep 1992
Conference number: 18
|Conference||18th European Solid-State Circuits Conference|
|Period||21/09/1992 → 23/09/1992|