A Network Traffic Generator Model for Fast Network-on-Chip Simulation

Shankar Mahadevan, Frederico Angiolini, Michael Storgaard, R. Olsen, Jens Sparsø, Jan Madsen

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    For Systems-on-Chip (SoCs) development, a predominant part of the design time is the simulation time. Performance evaluation and design space exploration of such systems in bit- and cycle-true fashion is becoming prohibitive. We propose a traffic generation (TG) model that provides a fast and effective Network-on-Chip (NoC) development and debugging environment. By capturing the type and the timestamp of communication events at the boundary of an IP core in a reference environment, the TG can subsequently emulate the core's communication behavior in different environments. Access patterns and resource contention in a system are dependent on the interconnect architecture, and our TG is designed to capture the resulting reactiveness. The regenerated traffic, which represents a realistic workload, can thus be used to undertake faster architectural exploration of interconnection alternatives, effectively decoupling simulation of IP cores and of interconnect fabrics. The results with the TG on an AMBA interconnect show a simulation time speedup above a factor of 2 over a complete system simulation, with close to 100% accuracy.
    Original languageEnglish
    Title of host publicationDesign, Automation and Test in Europe
    Publication date2005
    ISBN (Print)0-7695-2288-2
    Publication statusPublished - 2005
    Event2005 Design, Automation and Test in Europe Conference and Exposition - Munich, Germany
    Duration: 7 Mar 200511 Mar 2005


    Conference2005 Design, Automation and Test in Europe Conference and Exposition
    Internet address

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