A Multi-Format Floating-Point Multiplier for Power-Efficient Operations

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Abstract

In this work, we present a radix-16 multi-format multiplier to multiply 64-bit unsigned integer operands, doubleprecision and single-precision operands. The multiplier is sectioned in two lanes such that two single-precision multiplications can be computed in parallel. Radix-16 is chosen for the reduced number of partial products and the resulting power savings. The experimental results show that high power efficiency is obtained by issuing two single-precision multiplications per cycle. Moreover, by converting the double-precision numbers which fit to single-precision, further energy can be saved
Original languageEnglish
Title of host publicationProceedings of the 30th IEEE International System-on-Chip Conference
PublisherIEEE
Publication date2017
Pages351-356
ISBN (Print)9781538640333
DOIs
Publication statusPublished - 2017
Event30th IEEE International System-on-Chip Conference - München, Germany
Duration: 5 Sep 20178 Sep 2017

Conference

Conference30th IEEE International System-on-Chip Conference
CountryGermany
CityMünchen
Period05/09/201708/09/2017

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