A minimal network interface for a simple network-on-chip

Martin Schoeberl; Luca Pezzarossa; Jens Sparsø

doi:10.1007/978-3-030-18656-2_22

A minimal network interface for a simple network-on-chip

Martin Schoeberl^*
, Luca Pezzarossa
, Jens Sparsø

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Article in proceedings › Research › peer-review

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Abstract

Network-on-chip implementations are typically complex in the design of the routers and the network interfaces. The resource consumption of such routers and network interfaces approaches the size of an in-order processor pipeline. For the job of just moving data between processors, this may be considered too much overhead. This paper presents a lightweight network-on-chip solution. We build on the S4NOC for the router design and add a minimal network interface. The presented architecture supports the transfer of single words between all processor cores. Furthermore, as we use time-division multiplexing of the router and link resources, the latency of such transfers is upper bounded. Therefore, this network-on-chip can be used for real-time systems. The router and network interface together consume around 6% of the resources of a RISC processor pipeline.

Original language	English
Title of host publication	Architecture of Computing Systems - ARCS 2019
Editors	Martin Schoeberl, Thilo Pionteck, Sascha Uhrig, Jürgen Brehm, Christian Hochberger
Publisher	Springer
Publication date	1 Jan 2019
Pages	295-307
ISBN (Print)	9783030186555
DOIs	https://doi.org/10.1007/978-3-030-18656-2_22
Publication status	Published - 1 Jan 2019
Event	32nd International Conference on Architecture of Computing Systems - Copenhagen, Denmark Duration: 20 May 2019 → 23 May 2019 Conference number: 32

Conference

Conference	32nd International Conference on Architecture of Computing Systems
Number	32
Country/Territory	Denmark
City	Copenhagen
Period	20/05/2019 → 23/05/2019

Series	Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume	11479 LNCS
ISSN	0302-9743

Keywords

Communication
Multicore processor
Network interface
Network-on-chip
Real-time systems

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10.1007/978-3-030-18656-2_22

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Schoeberl, Martin ; Pezzarossa, Luca ; Sparsø, Jens. / A minimal network interface for a simple network-on-chip. Architecture of Computing Systems - ARCS 2019. editor / Martin Schoeberl ; Thilo Pionteck ; Sascha Uhrig ; Jürgen Brehm ; Christian Hochberger. Springer, 2019. pp. 295-307 (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), Vol. 11479 LNCS).

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title = "A minimal network interface for a simple network-on-chip",

abstract = "Network-on-chip implementations are typically complex in the design of the routers and the network interfaces. The resource consumption of such routers and network interfaces approaches the size of an in-order processor pipeline. For the job of just moving data between processors, this may be considered too much overhead. This paper presents a lightweight network-on-chip solution. We build on the S4NOC for the router design and add a minimal network interface. The presented architecture supports the transfer of single words between all processor cores. Furthermore, as we use time-division multiplexing of the router and link resources, the latency of such transfers is upper bounded. Therefore, this network-on-chip can be used for real-time systems. The router and network interface together consume around 6\% of the resources of a RISC processor pipeline.",

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author = "Martin Schoeberl and Luca Pezzarossa and Jens Spars{\o}",

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Schoeberl, M , Pezzarossa, L & Sparsø, J 2019, A minimal network interface for a simple network-on-chip. in M Schoeberl, T Pionteck, S Uhrig, J Brehm & C Hochberger (eds), Architecture of Computing Systems - ARCS 2019. Springer, Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), vol. 11479 LNCS, pp. 295-307, 32nd International Conference on Architecture of Computing Systems, Copenhagen, Denmark, 20/05/2019. https://doi.org/10.1007/978-3-030-18656-2_22

A minimal network interface for a simple network-on-chip. / Schoeberl, Martin ; Pezzarossa, Luca ; Sparsø, Jens.
Architecture of Computing Systems - ARCS 2019. ed. / Martin Schoeberl; Thilo Pionteck; Sascha Uhrig; Jürgen Brehm; Christian Hochberger. Springer, 2019. p. 295-307 (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), Vol. 11479 LNCS).

Research output: Chapter in Book/Report/Conference proceeding › Article in proceedings › Research › peer-review

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AU - Schoeberl, Martin

AU - Pezzarossa, Luca

AU - Sparsø, Jens

N1 - Conference code: 32

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N2 - Network-on-chip implementations are typically complex in the design of the routers and the network interfaces. The resource consumption of such routers and network interfaces approaches the size of an in-order processor pipeline. For the job of just moving data between processors, this may be considered too much overhead. This paper presents a lightweight network-on-chip solution. We build on the S4NOC for the router design and add a minimal network interface. The presented architecture supports the transfer of single words between all processor cores. Furthermore, as we use time-division multiplexing of the router and link resources, the latency of such transfers is upper bounded. Therefore, this network-on-chip can be used for real-time systems. The router and network interface together consume around 6% of the resources of a RISC processor pipeline.

AB - Network-on-chip implementations are typically complex in the design of the routers and the network interfaces. The resource consumption of such routers and network interfaces approaches the size of an in-order processor pipeline. For the job of just moving data between processors, this may be considered too much overhead. This paper presents a lightweight network-on-chip solution. We build on the S4NOC for the router design and add a minimal network interface. The presented architecture supports the transfer of single words between all processor cores. Furthermore, as we use time-division multiplexing of the router and link resources, the latency of such transfers is upper bounded. Therefore, this network-on-chip can be used for real-time systems. The router and network interface together consume around 6% of the resources of a RISC processor pipeline.

KW - Communication

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KW - Network interface

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KW - Real-time systems

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DO - 10.1007/978-3-030-18656-2_22

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T3 - Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

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BT - Architecture of Computing Systems - ARCS 2019

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Schoeberl M , Pezzarossa L , Sparsø J. A minimal network interface for a simple network-on-chip. In Schoeberl M, Pionteck T, Uhrig S, Brehm J, Hochberger C, editors, Architecture of Computing Systems - ARCS 2019. Springer. 2019. p. 295-307. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), Vol. 11479 LNCS). doi: 10.1007/978-3-030-18656-2_22

A minimal network interface for a simple network-on-chip

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Keywords

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