A minimal network interface for a simple network-on-chip

Martin Schoeberl*, Luca Pezzarossa, Jens Sparsø

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingArticle in proceedingsResearchpeer-review

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Network-on-chip implementations are typically complex in the design of the routers and the network interfaces. The resource consumption of such routers and network interfaces approaches the size of an in-order processor pipeline. For the job of just moving data between processors, this may be considered too much overhead. This paper presents a lightweight network-on-chip solution. We build on the S4NOC for the router design and add a minimal network interface. The presented architecture supports the transfer of single words between all processor cores. Furthermore, as we use time-division multiplexing of the router and link resources, the latency of such transfers is upper bounded. Therefore, this network-on-chip can be used for real-time systems. The router and network interface together consume around 6% of the resources of a RISC processor pipeline.

Original languageEnglish
Title of host publicationArchitecture of Computing Systems - ARCS 2019
EditorsMartin Schoeberl, Thilo Pionteck, Sascha Uhrig, Jürgen Brehm, Christian Hochberger
Publication date1 Jan 2019
ISBN (Print)9783030186555
Publication statusPublished - 1 Jan 2019
Event32nd International Conference on Architecture of Computing Systems - Copenhagen, Denmark
Duration: 20 May 201923 May 2019
Conference number: 32


Conference32nd International Conference on Architecture of Computing Systems
SeriesLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume11479 LNCS


  • Communication
  • Multicore processor
  • Network interface
  • Network-on-chip
  • Real-time systems


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