This paper describes a number of design issues relating to the implementation of low-power asynchronous signal processing circuits. Specifically, the paper addresses the design of a dedicated processor structure that implements an audio FIR filter bank which is part of an industrial application. The algorithm requires a fixed number of steps and the moderate speed requirement allows a sequential implementation. The latter, in combination with a huge predominance of numerically small data values in the input data stream, is the key to a low-power asynchronous implementation. Power is minimized in two ways: by reducing the switching activity in the circuit, and by applying adaptive scaling of the supply voltage, in order to exploit the fact that the average case latency as 2-3 times better than the worst case. The paper reports on a study of properties of real life data, and discusses the implications it has on the choice of architecture, handshake-protocol, data-encoding, and circuit design. This includes a tagging scheme that divides the data-path into slices, and an asynchronous ripple carry adder that avoids a completion tree.
|Title of host publication||Proceedings of the second International Symposium on Asynchronous Circuits and Systems|
|Publication status||Published - 1996|
|Event||2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems - Aizu, Japan|
Duration: 18 Mar 1996 → 21 Mar 1996
Conference number: 2
|Conference||2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems|
|Period||18/03/1996 → 21/03/1996|