A low-power 10-bit continuous-time CMOS ΣΔ A/D converter

Jannik Hammel Nielsen, Erik Bruun

Research output: Chapter in Book/Report/Conference proceedingArticle in proceedingsResearchpeer-review

394 Downloads (Pure)

Abstract

This paper presents the design of a third-order low-pass ΣΔ analog-to-digital converter (ADC) employing a continuous-time (CT) loop filter. The loop filter is implemented using Gm - C integrators, where the transconductors are implemented using CMOS transistors only. System level as well as transistor level design issues for power efficiency is discussed. A prototype ΣΔ ADC intended for weak biological signals restricted to bandwidths below 4 kHz has been manufactured in a standard 0.35 μm CMOS technology. The ADC has a measured resolution of 10 bits and a dynamic range (DR) of 67 dB at a sampling rate of fs = 1.4 MHz, while drawing a bias current of 60 μA from a modest supply voltage of 1.8 V, thus consuming 108 μW of power.
Original languageEnglish
Title of host publicationProceedings - IEEE International Symposium on Circuits and Systems
Volume1
PublisherIEEE
Publication date2004
Pages417-420
ISBN (Print)0-7803-8251-X
DOIs
Publication statusPublished - 2004
Event2004 IEEE International Symposium on Circuits and Systems - Vancouver, Canada
Duration: 23 May 200426 May 2004
http://www.cmsworldwide.com/ISCAS2004/

Conference

Conference2004 IEEE International Symposium on Circuits and Systems
Country/TerritoryCanada
CityVancouver
Period23/05/200426/05/2004
Internet address

Bibliographical note

Copyright: 2004 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE

Fingerprint

Dive into the research topics of 'A low-power 10-bit continuous-time CMOS ΣΔ A/D converter'. Together they form a unique fingerprint.

Cite this