A low-power 10-bit continuous-time CMOS ΣΔ A/D converter

Jannik Hammel Nielsen, Erik Bruun

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This paper presents the design of a third-order low-pass ΣΔ analog-to-digital converter (ADC) employing a continuous-time (CT) loop filter. The loop filter is implemented using Gm - C integrators, where the transconductors are implemented using CMOS transistors only. System level as well as transistor level design issues for power efficiency is discussed. A prototype ΣΔ ADC intended for weak biological signals restricted to bandwidths below 4 kHz has been manufactured in a standard 0.35 μm CMOS technology. The ADC has a measured resolution of 10 bits and a dynamic range (DR) of 67 dB at a sampling rate of fs = 1.4 MHz, while drawing a bias current of 60 μA from a modest supply voltage of 1.8 V, thus consuming 108 μW of power.
Original languageEnglish
Title of host publicationProceedings - IEEE International Symposium on Circuits and Systems
Publication date2004
ISBN (Print)0-7803-8251-X
Publication statusPublished - 2004
Event2004 IEEE International Symposium on Circuits and Systems - Vancouver, Canada
Duration: 23 May 200426 May 2004


Conference2004 IEEE International Symposium on Circuits and Systems
Internet address

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