A lock circuit for a multi-core processor

Research output: Patent

94 Downloads (Pure)


An integrated circuit comprising a multiple processor cores and a lock circuit that comprises a queue register with respective bits set or reset via respective, connections dedicated to respective processor cores, whereby the queue register identifies those among the multiple processor cores that are enqueued in the queue register. Furthermore, the integrated circuit comprises a current register and a selector circuit configured to select a processor core and identify that processor core by a value in the current register. A selected processor core is a prioritized processor core among the cores that have a bit that is set in the queue register. The processor cores are connected to receive a signal from the current register. Correspondingly: a method of synchronizing access to software and/or hardware resources by a core of a multi-core processor by means of a lock circuit; a multi-core processor configured with an integrated circuit; and a silicon die configured with an integrated circuit.

Original languageEnglish
IPCG06F 15/ 173 A I
Patent numberWO2015132293
Filing date11/09/2015
CountryInternational Bureau of the World Intellectual Property Organization (WIPO)
Priority date05/03/2014
Priority numberEP20140157808
Publication statusPublished - 11 Sep 2015

Cite this

Strøm, T. B. (2015). IPC No. G06F 15/ 173 A I. A lock circuit for a multi-core processor. (Patent No. WO2015132293).