A Light-Weight Statically Scheduled Network-on-Chip

Rasmus Bo Sørensen, Martin Schoeberl, Jens Sparsø

    Research output: Chapter in Book/Report/Conference proceedingArticle in proceedingsResearchpeer-review

    Abstract

    This paper investigates how a light-weight, statically scheduled network-on-chip (NoC) for real-time systems can be designed and implemented. The NoC provides communication channels between all cores with equal bandwidth and latency. The design is FPGA-friendly and consumes a minimum of resources. We implemented a 64 core 16-bit multiprocessor connected with the proposed NoC in a low-cost FPGA.
    Original languageEnglish
    Title of host publication2012 NORCHIP
    Number of pages6
    PublisherIEEE
    Publication date2012
    ISBN (Print)978-1-4673-2221-8
    ISBN (Electronic)978-1-4673-2222-5
    DOIs
    Publication statusPublished - 2012
    Event30th NORCHIP conference - Copenhagen, Denmark
    Duration: 12 Nov 201213 Nov 2012

    Conference

    Conference30th NORCHIP conference
    CountryDenmark
    CityCopenhagen
    Period12/11/201213/11/2012

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