A Light-Weight Statically Scheduled Network-on-Chip

Rasmus Bo Sørensen; Martin Schoeberl; Jens Sparsø

doi:10.1109/NORCHP.2012.6403129

A Light-Weight Statically Scheduled Network-on-Chip

Rasmus Bo Sørensen, Martin Schoeberl, Jens Sparsø

Research output: Chapter in Book/Report/Conference proceeding › Article in proceedings › Research › peer-review

Abstract

This paper investigates how a light-weight, statically scheduled network-on-chip (NoC) for real-time systems can be designed and implemented. The NoC provides communication channels between all cores with equal bandwidth and latency. The design is FPGA-friendly and consumes a minimum of resources. We implemented a 64 core 16-bit multiprocessor connected with the proposed NoC in a low-cost FPGA.

Original language	English
Title of host publication	2012 NORCHIP
Number of pages	6
Publisher	IEEE
Publication date	2012
ISBN (Print)	978-1-4673-2221-8
ISBN (Electronic)	978-1-4673-2222-5
DOIs	https://doi.org/10.1109/NORCHP.2012.6403129
Publication status	Published - 2012
Event	2012 IEEE 30th NORCHIP Conference - Hotel Richmond, Copenhagen, Denmark Duration: 12 Nov 2012 → 13 Nov 2013 Conference number: 30 https://ieeexplore.ieee.org/xpl/conhome/6385345/proceeding

Conference

Conference	2012 IEEE 30th NORCHIP Conference
Number	30
Location	Hotel Richmond
Country/Territory	Denmark
City	Copenhagen
Period	12/11/2012 → 13/11/2013
Internet address	https://ieeexplore.ieee.org/xpl/conhome/6385345/proceeding

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10.1109/NORCHP.2012.6403129

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title = "A Light-Weight Statically Scheduled Network-on-Chip",

abstract = "This paper investigates how a light-weight, statically scheduled network-on-chip (NoC) for real-time systems can be designed and implemented. The NoC provides communication channels between all cores with equal bandwidth and latency. The design is FPGA-friendly and consumes a minimum of resources. We implemented a 64 core 16-bit multiprocessor connected with the proposed NoC in a low-cost FPGA.",

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AB - This paper investigates how a light-weight, statically scheduled network-on-chip (NoC) for real-time systems can be designed and implemented. The NoC provides communication channels between all cores with equal bandwidth and latency. The design is FPGA-friendly and consumes a minimum of resources. We implemented a 64 core 16-bit multiprocessor connected with the proposed NoC in a low-cost FPGA.

U2 - 10.1109/NORCHP.2012.6403129

DO - 10.1109/NORCHP.2012.6403129

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PB - IEEE

T2 - 2012 IEEE 30th NORCHIP Conference

Y2 - 12 November 2012 through 13 November 2013

ER -

A Light-Weight Statically Scheduled Network-on-Chip

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