This paper investigates how a light-weight, statically scheduled network-on-chip (NoC) for real-time systems can be designed and implemented. The NoC provides communication channels between all cores with equal bandwidth and latency. The design is FPGA-friendly and consumes a minimum of resources. We implemented a 64 core 16-bit multiprocessor connected with the proposed NoC in a low-cost FPGA.
|Title of host publication||2012 NORCHIP|
|Number of pages||6|
|Publication status||Published - 2012|
|Event||30th NORCHIP conference - Copenhagen, Denmark|
Duration: 12 Nov 2012 → 13 Nov 2012
|Conference||30th NORCHIP conference|
|Period||12/11/2012 → 13/11/2012|