A high-speed interconnect network using ternary logic

Jens Kargaard Madsen, S. I. Long

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    Abstract

    This paper describes the design and implementation of a high-speed interconnect network (ICN) for a multiprocessor system using ternary logic. By using ternary logic and a fast point-to-point communication technique called STARI (Self-Timed At Receiver's Input), the communication between the processors is free of clock skew and insensitive to any delay differences in buffers and wires. In addition, the number of signal wires and pins are reduced by 50 percent in comparison with a similar binary implementation. The ICN architecture is based on a crossbar topology and the high-speed part consists of two LSI GaAs chips, Interface and Crossbar, which were implemented in a 0.8 μm MESFET process. In a 4×4 ICN, communication at 300 Mbit/s per wire was demonstrated, which is twice as fast as pure synchronous and four times faster than pure asynchronous communication in the specific test set-up
    Original languageEnglish
    Title of host publicationProceedings of the 25th International Symposium on Multiple-Valued Logic
    PublisherIEEE
    Publication date1995
    Pages2-7
    ISBN (Print)08-18-67118-1
    DOIs
    Publication statusPublished - 1995
    EventInternational Symposium on Multiple-Valued Logic - Bloomington, IN
    Duration: 1 Jan 1995 → …
    Conference number: 25th

    Conference

    ConferenceInternational Symposium on Multiple-Valued Logic
    Number25th
    CityBloomington, IN
    Period01/01/1995 → …

    Bibliographical note

    Copyright: 1995 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE

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