This paper describes a low-power programmable DSP architecture that targets audio signal processing. The architecture can be characterized as a heterogeneous multiprocessor consisting of small and simple instruction set processors called mini-cores that communicate using message passing. The processors are tailored for different classes of filtering algorithms (FIR, IIR, N-LMS etc.), and in a typical system the communication among processors occurs at the sampling rate only. The processors are parameterized in word-size, memory-size, etc. and can be instantiated according to the needs of the application at hand using a normal synthesis based ASIC design flow. To give an impression of the size of a processor we mention that one of the FIR processors in a prototype design has 16 instructions, a 32 word×16 bit program memory, a 64 word×16 bit data memory and a 25 word×16 bit coefficient memory. Early results obtained from the design of a prototype chip containing filter processors for a hearing aid application, indicate a power consumption that is an order of magnitude better than current state of the art low-power audio DSPs implemented using full-custom techniques. This is due to: (1) the small size of the processors and (2) a smaller instruction count for a given task.
|Title of host publication||Proceedings on IEEE Computer Society Workshop|
|Publication status||Published - 2001|
|Event||IEEE Computer Society Workshop - Orlando, FL|
Duration: 1 Jan 2001 → …
Conference number: 2001
|Conference||IEEE Computer Society Workshop|
|Period||01/01/2001 → …|