Abstract
This paper presents a low-power and programmable DSP architecture - a heterogeneous multiprocessor platform consisting of standard CPU/DSP cores, and a set of simple instruction set processors called mini-cores each optimized for a particular class of algorithm (FIR, IIR, LMS, etc.). Communication is based on message passing. The mini-cores are designed as parameterized soft macros intended for a synthesis based design flow. A 520.000 transistor 0.25µm CMOS prototype chip containing 6 mini-cores has been fabricated and tested. Its power consumption is only 50% higher than a hardwired ASIC and more than 6-21 times lower than a general purpose CPU/DSP corewhile executing non-trivial industrial applications.
Original language | English |
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Title of host publication | Proceedings of the 28th European Solid-State Circuits Conference, 2002. ESSCIRC 2002. |
Publisher | IEEE Press |
Publication date | 2002 |
ISBN (Print) | 88-900847-9-0 |
Publication status | Published - 2002 |
Event | 28th European Solid-State Circuits Conference - Florence, Italy Duration: 24 Sept 2002 → 26 Sept 2002 Conference number: 28 http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=9921 |
Conference
Conference | 28th European Solid-State Circuits Conference |
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Number | 28 |
Country/Territory | Italy |
City | Florence |
Period | 24/09/2002 → 26/09/2002 |
Internet address |