This paper presents a low-power and programmable DSP architecture - a heterogeneous multiprocessor platform consisting of standard CPU/DSP cores, and a set of simple instruction set processors called mini-cores each optimized for a particular class of algorithm (FIR, IIR, LMS, etc.). Communication is based on message passing. The mini-cores are designed as parameterized soft macros intended for a synthesis based design flow. A 520.000 transistor 0.25µm CMOS prototype chip containing 6 mini-cores has been fabricated and tested. Its power consumption is only 50% higher than a hardwired ASIC and more than 6-21 times lower than a general purpose CPU/DSP corewhile executing non-trivial industrial applications.
|Title of host publication||Proceedings of the 28th European Solid-State Circuits Conference, 2002. ESSCIRC 2002.|
|Publication status||Published - 2002|
|Event||28th European Solid-State Circuits Conference - Florence, Italy|
Duration: 24 Sep 2002 → 26 Sep 2002
Conference number: 28
|Conference||28th European Solid-State Circuits Conference|
|Period||24/09/2002 → 26/09/2002|
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Paker, O., Sparsø, J., Haandbæk, N., Isager, M., & Nielsen, L. S. (2002). A heterogeneous multi-core platform for low power signal processing in systems-on-chip. In Proceedings of the 28th European Solid-State Circuits Conference, 2002. ESSCIRC 2002. IEEE Press.