A heterogeneous multi-core platform for low power signal processing in systems-on-chip

Ozgun Paker; Jens Sparsø; Niels Haandbæk; Mogens Isager; Lars Skovby Nielsen

A heterogeneous multi-core platform for low power signal processing in systems-on-chip

Ozgun Paker, Jens Sparsø, Niels Haandbæk, Mogens Isager, Lars Skovby Nielsen

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Abstract

This paper presents a low-power and programmable DSP architecture - a heterogeneous multiprocessor platform consisting of standard CPU/DSP cores, and a set of simple instruction set processors called mini-cores each optimized for a particular class of algorithm (FIR, IIR, LMS, etc.). Communication is based on message passing. The mini-cores are designed as parameterized soft macros intended for a synthesis based design flow. A 520.000 transistor 0.25µm CMOS prototype chip containing 6 mini-cores has been fabricated and tested. Its power consumption is only 50% higher than a hardwired ASIC and more than 6-21 times lower than a general purpose CPU/DSP corewhile executing non-trivial industrial applications.

Original language	English
Title of host publication	Proceedings of the 28th European Solid-State Circuits Conference, 2002. ESSCIRC 2002.
Publisher	IEEE Press
Publication date	2002
ISBN (Print)	88-900847-9-0
Publication status	Published - 2002
Event	28th European Solid-State Circuits Conference - Florence, Italy Duration: 24 Sept 2002 → 26 Sept 2002 Conference number: 28 http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=9921

Conference

Conference	28th European Solid-State Circuits Conference
Number	28
Country/Territory	Italy
City	Florence
Period	24/09/2002 → 26/09/2002
Internet address	http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=9921

Bibliographical note

Copyright: 2002 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE

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title = "A heterogeneous multi-core platform for low power signal processing in systems-on-chip",

abstract = "This paper presents a low-power and programmable DSP architecture - a heterogeneous multiprocessor platform consisting of standard CPU/DSP cores, and a set of simple instruction set processors called mini-cores each optimized for a particular class of algorithm (FIR, IIR, LMS, etc.). Communication is based on message passing. The mini-cores are designed as parameterized soft macros intended for a synthesis based design flow. A 520.000 transistor 0.25µm CMOS prototype chip containing 6 mini-cores has been fabricated and tested. Its power consumption is only 50% higher than a hardwired ASIC and more than 6-21 times lower than a general purpose CPU/DSP corewhile executing non-trivial industrial applications.",

author = "Ozgun Paker and Jens Spars{\o} and Niels Haandb{\ae}k and Mogens Isager and Nielsen, {Lars Skovby}",

note = "Copyright: 2002 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE; 28th European Solid-State Circuits Conference, ESSCIRC 2002. ; Conference date: 24-09-2002 Through 26-09-2002",

year = "2002",

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AU - Paker, Ozgun

AU - Sparsø, Jens

AU - Haandbæk, Niels

AU - Isager, Mogens

AU - Nielsen, Lars Skovby

N1 - Conference code: 28

PY - 2002

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N2 - This paper presents a low-power and programmable DSP architecture - a heterogeneous multiprocessor platform consisting of standard CPU/DSP cores, and a set of simple instruction set processors called mini-cores each optimized for a particular class of algorithm (FIR, IIR, LMS, etc.). Communication is based on message passing. The mini-cores are designed as parameterized soft macros intended for a synthesis based design flow. A 520.000 transistor 0.25µm CMOS prototype chip containing 6 mini-cores has been fabricated and tested. Its power consumption is only 50% higher than a hardwired ASIC and more than 6-21 times lower than a general purpose CPU/DSP corewhile executing non-trivial industrial applications.

AB - This paper presents a low-power and programmable DSP architecture - a heterogeneous multiprocessor platform consisting of standard CPU/DSP cores, and a set of simple instruction set processors called mini-cores each optimized for a particular class of algorithm (FIR, IIR, LMS, etc.). Communication is based on message passing. The mini-cores are designed as parameterized soft macros intended for a synthesis based design flow. A 520.000 transistor 0.25µm CMOS prototype chip containing 6 mini-cores has been fabricated and tested. Its power consumption is only 50% higher than a hardwired ASIC and more than 6-21 times lower than a general purpose CPU/DSP corewhile executing non-trivial industrial applications.

M3 - Article in proceedings

SN - 88-900847-9-0

BT - Proceedings of the 28th European Solid-State Circuits Conference, 2002. ESSCIRC 2002.

PB - IEEE Press

T2 - 28th European Solid-State Circuits Conference

Y2 - 24 September 2002 through 26 September 2002

ER -

A heterogeneous multi-core platform for low power signal processing in systems-on-chip

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