A heterogeneous multi-core platform for low power signal processing in systems-on-chip

Ozgun Paker, Jens Sparsø, Niels Haandbæk, Mogens Isager, Lars Skovby Nielsen

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    This paper presents a low-power and programmable DSP architecture - a heterogeneous multiprocessor platform consisting of standard CPU/DSP cores, and a set of simple instruction set processors called mini-cores each optimized for a particular class of algorithm (FIR, IIR, LMS, etc.). Communication is based on message passing. The mini-cores are designed as parameterized soft macros intended for a synthesis based design flow. A 520.000 transistor 0.25µm CMOS prototype chip containing 6 mini-cores has been fabricated and tested. Its power consumption is only 50% higher than a hardwired ASIC and more than 6-21 times lower than a general purpose CPU/DSP corewhile executing non-trivial industrial applications.
    Original languageEnglish
    Title of host publicationProceedings of the 28th European Solid-State Circuits Conference, 2002. ESSCIRC 2002.
    PublisherIEEE Press
    Publication date2002
    ISBN (Print)88-900847-9-0
    Publication statusPublished - 2002
    Event28th European Solid-State Circuits Conference - Florence, Italy
    Duration: 24 Sept 200226 Sept 2002
    Conference number: 28


    Conference28th European Solid-State Circuits Conference
    Internet address

    Bibliographical note

    Copyright: 2002 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE


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