A Hardware Framework for on-Chip FPGA Acceleration

Andrea Lomuscio, Gian Carlo Cardarilli, Alberto Nannarelli, Marco Re

Research output: Chapter in Book/Report/Conference proceedingArticle in proceedingsResearchpeer-review

Abstract

In this work, we present a new framework to dynamically load hardware accelerators on reconfigurable platforms (FPGAs). Provided a library of application-specific processors, we load on-the-fly the specific processor in the FPGA, and we transfer the execution from the CPU to the FPGA-based accelerator. Results show that significant speed-up can be obtained by the proposed acceleration framework on system-on-chips where reconfigurable fabric is placed next to the CPUs. The speed-up is due to both the intrinsic acceleration in the application-specific processors, and to the increased parallelism.
Original languageEnglish
Title of host publicationProceedings of the 15th International Symposium on Integrated Circuits (ISIC 2016)
Number of pages4
PublisherIEEE
Publication date2016
ISBN (Print)978-1-4673-9019-4
DOIs
Publication statusPublished - 2016
Event15th International Symposium on Integrated Circuits - Resorts World Convention Centre, Singapore, Singapore
Duration: 12 Dec 201614 Dec 2016
Conference number: 15
http://www.isic-ieee.org/

Conference

Conference15th International Symposium on Integrated Circuits
Number15
LocationResorts World Convention Centre
Country/TerritorySingapore
CitySingapore
Period12/12/201614/12/2016
Internet address

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