A Hardware Framework for on-Chip FPGA Acceleration

Andrea  Lomuscio; Gian Carlo Cardarilli; Alberto Nannarelli; Marco Re

doi:10.1109/ISICIR.2016.7829683

A Hardware Framework for on-Chip FPGA Acceleration

Andrea Lomuscio, Gian Carlo Cardarilli, Alberto Nannarelli, Marco Re

University of Rome Tor Vergata

Research output: Chapter in Book/Report/Conference proceeding › Article in proceedings › Research › peer-review

Abstract

In this work, we present a new framework to dynamically load hardware accelerators on reconfigurable platforms (FPGAs). Provided a library of application-specific processors, we load on-the-fly the specific processor in the FPGA, and we transfer the execution from the CPU to the FPGA-based accelerator. Results show that significant speed-up can be obtained by the proposed acceleration framework on system-on-chips where reconfigurable fabric is placed next to the CPUs. The speed-up is due to both the intrinsic acceleration in the application-specific processors, and to the increased parallelism.

Original language	English
Title of host publication	Proceedings of the 15th International Symposium on Integrated Circuits (ISIC 2016)
Number of pages	4
Publisher	IEEE
Publication date	2016
ISBN (Print)	978-1-4673-9019-4
DOIs	https://doi.org/10.1109/ISICIR.2016.7829683
Publication status	Published - 2016
Event	15th International Symposium on Integrated Circuits - Resorts World Convention Centre, Singapore, Singapore Duration: 12 Dec 2016 → 14 Dec 2016 Conference number: 15 http://www.isic-ieee.org/

Conference

Conference	15th International Symposium on Integrated Circuits
Number	15
Location	Resorts World Convention Centre
Country/Territory	Singapore
City	Singapore
Period	12/12/2016 → 14/12/2016
Internet address	http://www.isic-ieee.org/

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10.1109/ISICIR.2016.7829683

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title = "A Hardware Framework for on-Chip FPGA Acceleration",

abstract = "In this work, we present a new framework to dynamically load hardware accelerators on reconfigurable platforms (FPGAs). Provided a library of application-specific processors, we load on-the-fly the specific processor in the FPGA, and we transfer the execution from the CPU to the FPGA-based accelerator. Results show that significant speed-up can be obtained by the proposed acceleration framework on system-on-chips where reconfigurable fabric is placed next to the CPUs. The speed-up is due to both the intrinsic acceleration in the application-specific processors, and to the increased parallelism.",

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AU - Cardarilli, Gian Carlo

AU - Nannarelli, Alberto

AU - Re, Marco

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AB - In this work, we present a new framework to dynamically load hardware accelerators on reconfigurable platforms (FPGAs). Provided a library of application-specific processors, we load on-the-fly the specific processor in the FPGA, and we transfer the execution from the CPU to the FPGA-based accelerator. Results show that significant speed-up can be obtained by the proposed acceleration framework on system-on-chips where reconfigurable fabric is placed next to the CPUs. The speed-up is due to both the intrinsic acceleration in the application-specific processors, and to the increased parallelism.

U2 - 10.1109/ISICIR.2016.7829683

DO - 10.1109/ISICIR.2016.7829683

M3 - Article in proceedings

SN - 978-1-4673-9019-4

BT - Proceedings of the 15th International Symposium on Integrated Circuits (ISIC 2016)

PB - IEEE

T2 - 15th International Symposium on Integrated Circuits

Y2 - 12 December 2016 through 14 December 2016

ER -

A Hardware Framework for on-Chip FPGA Acceleration

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