Abstract
In this work, we present a new framework to dynamically load hardware accelerators on reconfigurable platforms (FPGAs). Provided a library of application-specific processors, we load on-the-fly the specific processor in the FPGA, and we transfer the execution from the CPU to the FPGA-based accelerator. Results show that significant speed-up can be obtained by the proposed acceleration framework on system-on-chips where reconfigurable fabric is placed next to the CPUs. The speed-up is due to both the intrinsic acceleration in the application-specific processors, and to the increased parallelism.
Original language | English |
---|---|
Title of host publication | Proceedings of the 15th International Symposium on Integrated Circuits (ISIC 2016) |
Number of pages | 4 |
Publisher | IEEE |
Publication date | 2016 |
ISBN (Print) | 978-1-4673-9019-4 |
DOIs | |
Publication status | Published - 2016 |
Event | 15th International Symposium on Integrated Circuits - Resorts World Convention Centre, Singapore, Singapore Duration: 12 Dec 2016 → 14 Dec 2016 Conference number: 15 http://www.isic-ieee.org/ |
Conference
Conference | 15th International Symposium on Integrated Circuits |
---|---|
Number | 15 |
Location | Resorts World Convention Centre |
Country/Territory | Singapore |
City | Singapore |
Period | 12/12/2016 → 14/12/2016 |
Internet address |