A Fully Parallel VLSI-implementation of the Viterbi Decoding Algorithm

Jens Sparsø; Henrik Nordtorp Jørgensen; Erik Paaske; Steen Pedersen; Thomas Rübner-Petersen

A Fully Parallel VLSI-implementation of the Viterbi Decoding Algorithm

Jens Sparsø
, Henrik Nordtorp Jørgensen
, Erik Paaske
, Steen Pedersen
, Thomas Rübner-Petersen

Technical University of Denmark

Research output: Chapter in Book/Report/Conference proceeding › Article in proceedings › Research › peer-review

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Abstract

In this paper we describe the implementation of a K = 7, R = 1/2 single-chip Viterbi decoder intended to operate at 10-20 Mbit/sec. We propose a general, regular and area efficient floor-plan that is also suitable for implementation of decoders for codes with different generator polynomials or different values of K. The Shuffle-Exchange type interconnection network is implemented by organizing the 64 processing elements to form a ring. The ring is laid out in two columns, and the interconnections between non-neighbours are routed in the channel between the columns. The interconnection network occupies 32 % of the area, and the global signals (including power) occupy a further 10 %. A test-chip containing a pair of processing elements has been fabricated via NORCHIP (the Scandinavian CMOS IC prototype implementation service). This chip has been fully tested, and it operates correctly at speeds above 26 MHz under worst-case conditions (VDD = 4.75 V and TA = 70 Â°C).

Original language	English
Title of host publication	Proceedings of the 15th European Solid-State Circuits Conference
Publisher	IEEE
Publication date	1989
Pages	232-235
ISBN (Print)	3-85403-101-7
Publication status	Published - 1989
Event	15th European Solid-State Circuits Conference - Vienna, Austria Duration: 20 Sept 1989 → 22 Sept 1989 Conference number: 15 http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=5468015

Conference

Conference	15th European Solid-State Circuits Conference
Number	15
Country/Territory	Austria
City	Vienna
Period	20/09/1989 → 22/09/1989
Internet address	http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=5468015

Bibliographical note

Copyright 1989 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.

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@inproceedings{312042361bd64ec2a04c4b9bf092e401,

title = "A Fully Parallel VLSI-implementation of the Viterbi Decoding Algorithm",

abstract = "In this paper we describe the implementation of a K = 7, R = 1/2 single-chip Viterbi decoder intended to operate at 10-20 Mbit/sec. We propose a general, regular and area efficient floor-plan that is also suitable for implementation of decoders for codes with different generator polynomials or different values of K. The Shuffle-Exchange type interconnection network is implemented by organizing the 64 processing elements to form a ring. The ring is laid out in two columns, and the interconnections between non-neighbours are routed in the channel between the columns. The interconnection network occupies 32 \% of the area, and the global signals (including power) occupy a further 10 \%. A test-chip containing a pair of processing elements has been fabricated via NORCHIP (the Scandinavian CMOS IC prototype implementation service). This chip has been fully tested, and it operates correctly at speeds above 26 MHz under worst-case conditions (VDD = 4.75 V and TA = 70 {\^A}°C).",

author = "Jens Spars{\o} and J{\o}rgensen, \{Henrik Nordtorp\} and Erik Paaske and Steen Pedersen and Thomas R{\"u}bner-Petersen",

note = "Copyright 1989 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.; 15th European Solid-State Circuits Conference, ESSCIRC '89. ; Conference date: 20-09-1989 Through 22-09-1989",

year = "1989",

language = "English",

isbn = "3-85403-101-7",

pages = "232--235",

booktitle = "Proceedings of the 15th European Solid-State Circuits Conference",

publisher = "IEEE",

address = "United States",

url = "http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=5468015",

}

TY - GEN

T1 - A Fully Parallel VLSI-implementation of the Viterbi Decoding Algorithm

AU - Sparsø, Jens

AU - Jørgensen, Henrik Nordtorp

AU - Paaske, Erik

AU - Pedersen, Steen

AU - Rübner-Petersen, Thomas

N1 - Conference code: 15

PY - 1989

Y1 - 1989

N2 - In this paper we describe the implementation of a K = 7, R = 1/2 single-chip Viterbi decoder intended to operate at 10-20 Mbit/sec. We propose a general, regular and area efficient floor-plan that is also suitable for implementation of decoders for codes with different generator polynomials or different values of K. The Shuffle-Exchange type interconnection network is implemented by organizing the 64 processing elements to form a ring. The ring is laid out in two columns, and the interconnections between non-neighbours are routed in the channel between the columns. The interconnection network occupies 32 % of the area, and the global signals (including power) occupy a further 10 %. A test-chip containing a pair of processing elements has been fabricated via NORCHIP (the Scandinavian CMOS IC prototype implementation service). This chip has been fully tested, and it operates correctly at speeds above 26 MHz under worst-case conditions (VDD = 4.75 V and TA = 70 Â°C).

AB - In this paper we describe the implementation of a K = 7, R = 1/2 single-chip Viterbi decoder intended to operate at 10-20 Mbit/sec. We propose a general, regular and area efficient floor-plan that is also suitable for implementation of decoders for codes with different generator polynomials or different values of K. The Shuffle-Exchange type interconnection network is implemented by organizing the 64 processing elements to form a ring. The ring is laid out in two columns, and the interconnections between non-neighbours are routed in the channel between the columns. The interconnection network occupies 32 % of the area, and the global signals (including power) occupy a further 10 %. A test-chip containing a pair of processing elements has been fabricated via NORCHIP (the Scandinavian CMOS IC prototype implementation service). This chip has been fully tested, and it operates correctly at speeds above 26 MHz under worst-case conditions (VDD = 4.75 V and TA = 70 Â°C).

M3 - Article in proceedings

SN - 3-85403-101-7

SP - 232

EP - 235

BT - Proceedings of the 15th European Solid-State Circuits Conference

PB - IEEE

T2 - 15th European Solid-State Circuits Conference

Y2 - 20 September 1989 through 22 September 1989

ER -

A Fully Parallel VLSI-implementation of the Viterbi Decoding Algorithm

Abstract

Conference

Bibliographical note

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