A Framework for Dynamically-Loaded Hardware Library (HLL) in FPGA Acceleration

Gian Carlo Cardarilli; Leonardo  Di Carlo; Alberto Nannarelli; Federico Maria  Pandolfi; Marco Re

doi:10.1109/ISSPIT.2015.7394346

A Framework for Dynamically-Loaded Hardware Library (HLL) in FPGA Acceleration

Gian Carlo Cardarilli, Leonardo Di Carlo, Alberto Nannarelli, Federico Maria Pandolfi, Marco Re

University of Rome Tor Vergata

Research output: Chapter in Book/Report/Conference proceeding › Article in proceedings › Research › peer-review

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Abstract

Hardware acceleration is often used to address the need for speed and computing power in embedded systems. FPGAs always represented a good solution for HW acceleration and, recently, new SoC platforms extended the flexibility of the FPGAs by combining on a single chip both high-performance CPUs and FPGA fabric.

The aim of this work is the implementation of hardware accelerators for these new SoCs. The innovative feature of these accelerators is the on-the-fly reconfiguration of the hardware to dynamically adapt the accelerator’s functionalities to the current CPU workload. The realization of the accelerators preliminarily requires also the profiling of both the SW (ARM CPU + NEON Units) and HW (FPGA) performance, an evaluation of the partial reconfiguration times and the development of an applicationspecific IP-cores library.

This paper focuses on the profiling aspect of both the SW and HW implementation of the same operations, using arithmetic routines (BLAS) as the reference point for benchmarking, and presents a comparison of the results in terms of speed, power consumption and resources utilization.

Original language	English
Title of host publication	Proceedings of the 15th IEEE International Symposium on Signal Processing and Information Technology (ISSPIT 2015)
Publisher	IEEE
Publication date	2016
Pages	291-296
ISBN (Print)	978-1-5090-0480-5
DOIs	https://doi.org/10.1109/ISSPIT.2015.7394346
Publication status	Published - 2016
Event	15th IEEE International Symposium on Signal Processing and Information Technology (ISSPIT 2015) - Abu Dhabi, United Arab Emirates Duration: 7 Dec 2015 → 10 Dec 2015 Conference number: 15 http://ece.adu.ac.ae/ISSPIT2015/index.html

Conference

Conference	15th IEEE International Symposium on Signal Processing and Information Technology (ISSPIT 2015)
Number	15
Country/Territory	United Arab Emirates
City	Abu Dhabi
Period	07/12/2015 → 10/12/2015
Internet address	http://ece.adu.ac.ae/ISSPIT2015/index.html

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title = "A Framework for Dynamically-Loaded Hardware Library (HLL) in FPGA Acceleration",

abstract = "Hardware acceleration is often used to address the need for speed and computing power in embedded systems. FPGAs always represented a good solution for HW acceleration and, recently, new SoC platforms extended the flexibility of the FPGAs by combining on a single chip both high-performance CPUs and FPGA fabric.The aim of this work is the implementation of hardware accelerators for these new SoCs. The innovative feature of these accelerators is the on-the-fly reconfiguration of the hardware to dynamically adapt the accelerator{\textquoteright}s functionalities to the current CPU workload. The realization of the accelerators preliminarily requires also the profiling of both the SW (ARM CPU + NEON Units) and HW (FPGA) performance, an evaluation of the partial reconfiguration times and the development of an applicationspecific IP-cores library.This paper focuses on the profiling aspect of both the SW and HW implementation of the same operations, using arithmetic routines (BLAS) as the reference point for benchmarking, and presents a comparison of the results in terms of speed, power consumption and resources utilization.",

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address = "United States",

note = "15th IEEE International Symposium on Signal Processing and Information Technology (ISSPIT 2015), IEEE ISSPIT ; Conference date: 07-12-2015 Through 10-12-2015",

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}

Cardarilli, GC, Di Carlo, L, Nannarelli, A, Pandolfi, FM & Re, M 2016, A Framework for Dynamically-Loaded Hardware Library (HLL) in FPGA Acceleration. in Proceedings of the 15th IEEE International Symposium on Signal Processing and Information Technology (ISSPIT 2015). IEEE, pp. 291-296, 15th IEEE International Symposium on Signal Processing and Information Technology (ISSPIT 2015), Abu Dhabi, United Arab Emirates, 07/12/2015. https://doi.org/10.1109/ISSPIT.2015.7394346

A Framework for Dynamically-Loaded Hardware Library (HLL) in FPGA Acceleration. / Cardarilli, Gian Carlo; Di Carlo, Leonardo ; Nannarelli, Alberto et al.
Proceedings of the 15th IEEE International Symposium on Signal Processing and Information Technology (ISSPIT 2015). IEEE, 2016. p. 291-296.

Research output: Chapter in Book/Report/Conference proceeding › Article in proceedings › Research › peer-review

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A Framework for Dynamically-Loaded Hardware Library (HLL) in FPGA Acceleration

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