A Design Methodology for Power-efficient Continuous-time Sigma-Delta A/D Converters

Jannik Hammel Nielsen; Erik Bruun

A Design Methodology for Power-efficient Continuous-time Sigma-Delta A/D Converters

Jannik Hammel Nielsen, Erik Bruun

Research output: Chapter in Book/Report/Conference proceeding › Article in proceedings › Research › peer-review

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Abstract

In this paper we present a design methodology for optimizing the power consumption of continuous-time (CT) ΣΔ A/D converters. A method for performance prediction for ΣΔ A/D converters is presented. Estimation of analog and digital power consumption is derived and employed to predict the most power efficient configuration of a CT single-loop ΣΔ ADC. Finally, a 10 bit prototype converter is optimized and simulated using a 0.35 μm CMOS technology. The simulation results of the prototype 1.8 V converter show a SNR better than 65 dB and a spurious-free dynamic range of more than 63dB, consistent with 10 bits performance. Expected power consumption for the prototype is approx. 170 μW.

Original language	English
Title of host publication	Proceedings IEEE International Symposium on Circuits and Systems
Publisher	IEEE
Publication date	2003
Pages	1069-1072
ISBN (Print)	0-7803-7761-3
Publication status	Published - 2003
Event	2003 IEEE International Symposium on Circuits and Systems - Bangkok, Thailand Duration: 25 May 2003 → 28 May 2003 http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=8570

Conference

Conference	2003 IEEE International Symposium on Circuits and Systems
Country/Territory	Thailand
City	Bangkok
Period	25/05/2003 → 28/05/2003
Internet address	http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=8570

Bibliographical note

Copyright: 2003 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE

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title = "A Design Methodology for Power-efficient Continuous-time Sigma-Delta A/D Converters",

abstract = "In this paper we present a design methodology for optimizing the power consumption of continuous-time (CT) ΣΔ A/D converters. A method for performance prediction for ΣΔ A/D converters is presented. Estimation of analog and digital power consumption is derived and employed to predict the most power efficient configuration of a CT single-loop ΣΔ ADC. Finally, a 10 bit prototype converter is optimized and simulated using a 0.35 μm CMOS technology. The simulation results of the prototype 1.8 V converter show a SNR better than 65 dB and a spurious-free dynamic range of more than 63dB, consistent with 10 bits performance. Expected power consumption for the prototype is approx. 170 μW.",

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N2 - In this paper we present a design methodology for optimizing the power consumption of continuous-time (CT) ΣΔ A/D converters. A method for performance prediction for ΣΔ A/D converters is presented. Estimation of analog and digital power consumption is derived and employed to predict the most power efficient configuration of a CT single-loop ΣΔ ADC. Finally, a 10 bit prototype converter is optimized and simulated using a 0.35 μm CMOS technology. The simulation results of the prototype 1.8 V converter show a SNR better than 65 dB and a spurious-free dynamic range of more than 63dB, consistent with 10 bits performance. Expected power consumption for the prototype is approx. 170 μW.

AB - In this paper we present a design methodology for optimizing the power consumption of continuous-time (CT) ΣΔ A/D converters. A method for performance prediction for ΣΔ A/D converters is presented. Estimation of analog and digital power consumption is derived and employed to predict the most power efficient configuration of a CT single-loop ΣΔ ADC. Finally, a 10 bit prototype converter is optimized and simulated using a 0.35 μm CMOS technology. The simulation results of the prototype 1.8 V converter show a SNR better than 65 dB and a spurious-free dynamic range of more than 63dB, consistent with 10 bits performance. Expected power consumption for the prototype is approx. 170 μW.

M3 - Article in proceedings

SN - 0-7803-7761-3

SP - 1069

EP - 1072

BT - Proceedings IEEE International Symposium on Circuits and Systems

PB - IEEE

T2 - 2003 IEEE International Symposium on Circuits and Systems

Y2 - 25 May 2003 through 28 May 2003

ER -

A Design Methodology for Power-efficient Continuous-time Sigma-Delta A/D Converters

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