A Design Methodology for Power-efficient Continuous-time Sigma-Delta A/D Converters

Jannik Hammel Nielsen, Erik Bruun

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Abstract

In this paper we present a design methodology for optimizing the power consumption of continuous-time (CT) ΣΔ A/D converters. A method for performance prediction for ΣΔ A/D converters is presented. Estimation of analog and digital power consumption is derived and employed to predict the most power efficient configuration of a CT single-loop ΣΔ ADC. Finally, a 10 bit prototype converter is optimized and simulated using a 0.35 μm CMOS technology. The simulation results of the prototype 1.8 V converter show a SNR better than 65 dB and a spurious-free dynamic range of more than 63dB, consistent with 10 bits performance. Expected power consumption for the prototype is approx. 170 μW.
Original languageEnglish
Title of host publicationProceedings IEEE International Symposium on Circuits and Systems
PublisherIEEE
Publication date2003
Pages1069-1072
ISBN (Print)0-7803-7761-3
Publication statusPublished - 2003
Event2003 IEEE International Symposium on Circuits and Systems - Bangkok, Thailand
Duration: 25 May 200328 May 2003
http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=8570

Conference

Conference2003 IEEE International Symposium on Circuits and Systems
CountryThailand
CityBangkok
Period25/05/200328/05/2003
Internet address

Bibliographical note

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