In this paper we present a design methodology for optimizing the power consumption of continuous-time (CT) ΣΔ A/D converters. A method for performance prediction for ΣΔ A/D converters is presented. Estimation of analog and digital power consumption is derived and employed to predict the most power efficient configuration of a CT single-loop ΣΔ ADC. Finally, a 10 bit prototype converter is optimized and simulated using a 0.35 μm CMOS technology. The simulation results of the prototype 1.8 V converter show a SNR better than 65 dB and a spurious-free dynamic range of more than 63dB, consistent with 10 bits performance. Expected power consumption for the prototype is approx. 170 μW.
|Title of host publication||Proceedings IEEE International Symposium on Circuits and Systems|
|Publication status||Published - 2003|
|Event||2003 IEEE International Symposium on Circuits and Systems - Bangkok, Thailand|
Duration: 25 May 2003 → 28 May 2003
|Conference||2003 IEEE International Symposium on Circuits and Systems|
|Period||25/05/2003 → 28/05/2003|