A Controller for Dynamic Partial Reconfiguration in FPGA-Based Real-Time Systems

Research output: Chapter in Book/Report/Conference proceedingArticle in proceedingsResearchpeer-review

1 Downloads (Pure)

Abstract

In real-time systems, the use of hardware accelerators can lead to a worst-case execution-time speed-up, to a simplification of its analysis, and to a reduction of its pessimism. When using FPGA technology, dynamic partial reconfiguration (DPR) can be used to minimize the area, by only loading those accelerators that are needed at any given point in time. The DPR controllers provided by the FPGA vendors satisfy a wide range of requirements and rely on software to manage the reconfiguration. This approach may lead to slow reconfiguration and unpredictable timing. This paper presents an open-source DPR controller specially developed for hard real-time systems and prototyped in connection with the open-source multi-core platform for real-time applications T-CREST. The controller enables a processor to perform reconfiguration in a time-predictable manner and supports different operating modes. The paper also presents a software tool for bitstream conversion, compression, and for reconfiguration time analysis. The DPR controller is evaluated in terms of hardware cost, operating frequency, speed, and bitstream compression ratio vs. reconfiguration time trade-off. A simple application example is also presented with the scope of showing the reconfiguration features of the controller.
Original languageEnglish
Title of host publication2017 IEEE 20th International Symposium on Real-Time Distributed Computing
PublisherIEEE
Publication date2017
Pages92-100
DOIs
Publication statusPublished - 2017
Event2017 IEEE 20th International Symposium on Real-Time Distributed Computing - Fields Institute, Toronto, Canada
Duration: 16 May 201718 May 2017

Conference

Conference2017 IEEE 20th International Symposium on Real-Time Distributed Computing
LocationFields Institute
CountryCanada
CityToronto
Period16/05/201718/05/2017
Series2017 Ieee 20th International Symposium on Real-time Distributed Computing (isorc). Proceedings
ISSN2375-5261

Keywords

  • Logic circuits
  • Logic and switching circuits
  • Field programmable gate arrays
  • Real-time systems
  • Dynamic partial reconfiguration
  • FPGA-based real-time systems
  • Open-source DPR controller
  • Open-source multicore platform
  • Software tool
  • Hardware
  • Process control
  • Computer architecture
  • Software
  • Random access memory
  • Reconfiguration controller
  • Reconfiguration time analysis
  • T-CREST multi-core platform
  • Reconfiguration application example

Cite this

Pezzarossa, L., Schoeberl, M., & Sparsø, J. (2017). A Controller for Dynamic Partial Reconfiguration in FPGA-Based Real-Time Systems. In 2017 IEEE 20th International Symposium on Real-Time Distributed Computing (pp. 92-100). IEEE. 2017 Ieee 20th International Symposium on Real-time Distributed Computing (isorc). Proceedings https://doi.org/10.1109/ISORC.2017.3
Pezzarossa, Luca ; Schoeberl, Martin ; Sparsø, Jens. / A Controller for Dynamic Partial Reconfiguration in FPGA-Based Real-Time Systems. 2017 IEEE 20th International Symposium on Real-Time Distributed Computing. IEEE, 2017. pp. 92-100 (2017 Ieee 20th International Symposium on Real-time Distributed Computing (isorc). Proceedings).
@inproceedings{cc530c52dce34b229b31f053d2b072de,
title = "A Controller for Dynamic Partial Reconfiguration in FPGA-Based Real-Time Systems",
abstract = "In real-time systems, the use of hardware accelerators can lead to a worst-case execution-time speed-up, to a simplification of its analysis, and to a reduction of its pessimism. When using FPGA technology, dynamic partial reconfiguration (DPR) can be used to minimize the area, by only loading those accelerators that are needed at any given point in time. The DPR controllers provided by the FPGA vendors satisfy a wide range of requirements and rely on software to manage the reconfiguration. This approach may lead to slow reconfiguration and unpredictable timing. This paper presents an open-source DPR controller specially developed for hard real-time systems and prototyped in connection with the open-source multi-core platform for real-time applications T-CREST. The controller enables a processor to perform reconfiguration in a time-predictable manner and supports different operating modes. The paper also presents a software tool for bitstream conversion, compression, and for reconfiguration time analysis. The DPR controller is evaluated in terms of hardware cost, operating frequency, speed, and bitstream compression ratio vs. reconfiguration time trade-off. A simple application example is also presented with the scope of showing the reconfiguration features of the controller.",
keywords = "Logic circuits, Logic and switching circuits, Field programmable gate arrays, Real-time systems, Dynamic partial reconfiguration, FPGA-based real-time systems, Open-source DPR controller, Open-source multicore platform, Software tool, Hardware, Process control, Computer architecture, Software, Random access memory, Reconfiguration controller, Reconfiguration time analysis, T-CREST multi-core platform, Reconfiguration application example",
author = "Luca Pezzarossa and Martin Schoeberl and Jens Spars{\o}",
year = "2017",
doi = "10.1109/ISORC.2017.3",
language = "English",
pages = "92--100",
booktitle = "2017 IEEE 20th International Symposium on Real-Time Distributed Computing",
publisher = "IEEE",
address = "United States",

}

Pezzarossa, L, Schoeberl, M & Sparsø, J 2017, A Controller for Dynamic Partial Reconfiguration in FPGA-Based Real-Time Systems. in 2017 IEEE 20th International Symposium on Real-Time Distributed Computing. IEEE, 2017 Ieee 20th International Symposium on Real-time Distributed Computing (isorc). Proceedings, pp. 92-100, 2017 IEEE 20th International Symposium on Real-Time Distributed Computing, Toronto, Canada, 16/05/2017. https://doi.org/10.1109/ISORC.2017.3

A Controller for Dynamic Partial Reconfiguration in FPGA-Based Real-Time Systems. / Pezzarossa, Luca; Schoeberl, Martin; Sparsø, Jens.

2017 IEEE 20th International Symposium on Real-Time Distributed Computing. IEEE, 2017. p. 92-100 (2017 Ieee 20th International Symposium on Real-time Distributed Computing (isorc). Proceedings).

Research output: Chapter in Book/Report/Conference proceedingArticle in proceedingsResearchpeer-review

TY - GEN

T1 - A Controller for Dynamic Partial Reconfiguration in FPGA-Based Real-Time Systems

AU - Pezzarossa, Luca

AU - Schoeberl, Martin

AU - Sparsø, Jens

PY - 2017

Y1 - 2017

N2 - In real-time systems, the use of hardware accelerators can lead to a worst-case execution-time speed-up, to a simplification of its analysis, and to a reduction of its pessimism. When using FPGA technology, dynamic partial reconfiguration (DPR) can be used to minimize the area, by only loading those accelerators that are needed at any given point in time. The DPR controllers provided by the FPGA vendors satisfy a wide range of requirements and rely on software to manage the reconfiguration. This approach may lead to slow reconfiguration and unpredictable timing. This paper presents an open-source DPR controller specially developed for hard real-time systems and prototyped in connection with the open-source multi-core platform for real-time applications T-CREST. The controller enables a processor to perform reconfiguration in a time-predictable manner and supports different operating modes. The paper also presents a software tool for bitstream conversion, compression, and for reconfiguration time analysis. The DPR controller is evaluated in terms of hardware cost, operating frequency, speed, and bitstream compression ratio vs. reconfiguration time trade-off. A simple application example is also presented with the scope of showing the reconfiguration features of the controller.

AB - In real-time systems, the use of hardware accelerators can lead to a worst-case execution-time speed-up, to a simplification of its analysis, and to a reduction of its pessimism. When using FPGA technology, dynamic partial reconfiguration (DPR) can be used to minimize the area, by only loading those accelerators that are needed at any given point in time. The DPR controllers provided by the FPGA vendors satisfy a wide range of requirements and rely on software to manage the reconfiguration. This approach may lead to slow reconfiguration and unpredictable timing. This paper presents an open-source DPR controller specially developed for hard real-time systems and prototyped in connection with the open-source multi-core platform for real-time applications T-CREST. The controller enables a processor to perform reconfiguration in a time-predictable manner and supports different operating modes. The paper also presents a software tool for bitstream conversion, compression, and for reconfiguration time analysis. The DPR controller is evaluated in terms of hardware cost, operating frequency, speed, and bitstream compression ratio vs. reconfiguration time trade-off. A simple application example is also presented with the scope of showing the reconfiguration features of the controller.

KW - Logic circuits

KW - Logic and switching circuits

KW - Field programmable gate arrays

KW - Real-time systems

KW - Dynamic partial reconfiguration

KW - FPGA-based real-time systems

KW - Open-source DPR controller

KW - Open-source multicore platform

KW - Software tool

KW - Hardware

KW - Process control

KW - Computer architecture

KW - Software

KW - Random access memory

KW - Reconfiguration controller

KW - Reconfiguration time analysis

KW - T-CREST multi-core platform

KW - Reconfiguration application example

U2 - 10.1109/ISORC.2017.3

DO - 10.1109/ISORC.2017.3

M3 - Article in proceedings

SP - 92

EP - 100

BT - 2017 IEEE 20th International Symposium on Real-Time Distributed Computing

PB - IEEE

ER -

Pezzarossa L, Schoeberl M, Sparsø J. A Controller for Dynamic Partial Reconfiguration in FPGA-Based Real-Time Systems. In 2017 IEEE 20th International Symposium on Real-Time Distributed Computing. IEEE. 2017. p. 92-100. (2017 Ieee 20th International Symposium on Real-time Distributed Computing (isorc). Proceedings). https://doi.org/10.1109/ISORC.2017.3