A configurable FPGA FEC unit for Tb/s optical communication

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Abstract

Decoding of FEC (forward error correction) for optical communication beyond 1 Tb/s is investigated. A configurable single FPGA solution is presented having configurations supporting bit-rates in the range from 40 Gb/s to 1.6 Tb/s. The design allows for trade-offs of bit-rate, footprint, and latency within the resources of the FPGA. A proof-of-concept lab experiment at 40 Gb/s was conducted and pre-FEC — post-FEC performance validated with simulated results.
Original languageEnglish
Title of host publicationProceedings of 2017 IEEE International Conference on Communications
Number of pages6
PublisherIEEE
Publication date2017
Pages1-6
ISBN (Print)9781467389990
DOIs
Publication statusPublished - 2017
Event2017 IEEE International Conference on Communications - Palais des Congrès - Porte Maillot, Paris, France
Duration: 21 May 201725 May 2017

Conference

Conference2017 IEEE International Conference on Communications
LocationPalais des Congrès - Porte Maillot
CountryFrance
CityParis
Period21/05/201725/05/2017
SeriesI E E E International Conference on Communications
ISSN1550-3607

Keywords

  • Optical fiber networks
  • HD-FEC
  • Beyond 1 Tb/s
  • Product codes
  • Optical communication

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