Abstract
| Original language | English |
|---|---|
| Title of host publication | Proceedings of 2017 IEEE International Conference on Communications |
| Number of pages | 6 |
| Publisher | IEEE |
| Publication date | 2017 |
| Pages | 1-6 |
| ISBN (Print) | 9781467389990 |
| DOIs | |
| Publication status | Published - 2017 |
| Event | 2017 IEEE International Conference on Communications - Palais des Congrès - Porte Maillot, Paris, France Duration: 21 May 2017 → 25 May 2017 |
Conference
| Conference | 2017 IEEE International Conference on Communications |
|---|---|
| Location | Palais des Congrès - Porte Maillot |
| Country | France |
| City | Paris |
| Period | 21/05/2017 → 25/05/2017 |
| Series | I E E E International Conference on Communications |
|---|---|
| ISSN | 1550-3607 |
Keywords
- Optical fiber networks
- HD-FEC
- Beyond 1 Tb/s
- Product codes
- Optical communication
Cite this
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A configurable FPGA FEC unit for Tb/s optical communication. / Andersen, Jakob Dahl; Larsen, Knud J.; Bering Bøgh, Christian; Forchhammer, Søren; Da Ros, Francesco; Dalgaard, Kjeld; Iqbal, Shajeel.
Proceedings of 2017 IEEE International Conference on Communications. IEEE, 2017. p. 1-6 (I E E E International Conference on Communications).Research output: Chapter in Book/Report/Conference proceeding › Article in proceedings › Research › peer-review
TY - GEN
T1 - A configurable FPGA FEC unit for Tb/s optical communication
AU - Andersen, Jakob Dahl
AU - Larsen, Knud J.
AU - Bering Bøgh, Christian
AU - Forchhammer, Søren
AU - Da Ros, Francesco
AU - Dalgaard, Kjeld
AU - Iqbal, Shajeel
PY - 2017
Y1 - 2017
N2 - Decoding of FEC (forward error correction) for optical communication beyond 1 Tb/s is investigated. A configurable single FPGA solution is presented having configurations supporting bit-rates in the range from 40 Gb/s to 1.6 Tb/s. The design allows for trade-offs of bit-rate, footprint, and latency within the resources of the FPGA. A proof-of-concept lab experiment at 40 Gb/s was conducted and pre-FEC — post-FEC performance validated with simulated results.
AB - Decoding of FEC (forward error correction) for optical communication beyond 1 Tb/s is investigated. A configurable single FPGA solution is presented having configurations supporting bit-rates in the range from 40 Gb/s to 1.6 Tb/s. The design allows for trade-offs of bit-rate, footprint, and latency within the resources of the FPGA. A proof-of-concept lab experiment at 40 Gb/s was conducted and pre-FEC — post-FEC performance validated with simulated results.
KW - Optical fiber networks
KW - HD-FEC
KW - Beyond 1 Tb/s
KW - Product codes
KW - Optical communication
U2 - 10.1109/ICC.2017.7996767
DO - 10.1109/ICC.2017.7996767
M3 - Article in proceedings
SN - 9781467389990
SP - 1
EP - 6
BT - Proceedings of 2017 IEEE International Conference on Communications
PB - IEEE
ER -