A codesign case study: implementing arithmetic functions in FPGAs

I. V. Klotchkov; Steen Pedersen

doi:10.1109/ECBS.1996.494565

A codesign case study: implementing arithmetic functions in FPGAs

I. V. Klotchkov, Steen Pedersen

Technical University of Denmark

Research output: Chapter in Book/Report/Conference proceeding › Article in proceedings › Research › peer-review

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Abstract

Different ways of implementing and designing arithmetic functions for 16/32 bit integers in FPGA technology are studied. A comparison of four different design methods is also included. The results are used to increase the overall system performance in a dedicated 3D image analysis prototype system by moving a vector length calculation from software to hardware. The conclusion is that by adding one relatively simple board containing two FPGAs in the prototype setup, the total computing time is reduced by 30%. The total amount of image data, in this case 300 Mbyte, which has to be transmitted via the network is reduced by a factor of two, and the required network bandwidth is reduced similarly

Original language	English
Title of host publication	Proceedings of the IEEE Symposium and Workshop on Engineering of Computer-Based Systems
Publisher	IEEE
Publication date	1996
Pages	389-394
ISBN (Print)	08-18-67355-9
DOIs	https://doi.org/10.1109/ECBS.1996.494565
Publication status	Published - 1996
Event	1996 IEEE Symposium and Workshop on Engineering of Computer-Based Systems - Friedrichshafen, Germany Duration: 11 Mar 1996 → 15 Mar 1996 https://ieeexplore.ieee.org/xpl/conhome/3565/proceeding

Conference

Conference	1996 IEEE Symposium and Workshop on Engineering of Computer-Based Systems
Country/Territory	Germany
City	Friedrichshafen
Period	11/03/1996 → 15/03/1996
Internet address	https://ieeexplore.ieee.org/xpl/conhome/3565/proceeding

Bibliographical note

Copyright: 1996 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE

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10.1109/ECBS.1996.494565

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@inproceedings{6e724aa978494156b98081d712aabddc,

title = "A codesign case study: implementing arithmetic functions in FPGAs",

abstract = "Different ways of implementing and designing arithmetic functions for 16/32 bit integers in FPGA technology are studied. A comparison of four different design methods is also included. The results are used to increase the overall system performance in a dedicated 3D image analysis prototype system by moving a vector length calculation from software to hardware. The conclusion is that by adding one relatively simple board containing two FPGAs in the prototype setup, the total computing time is reduced by 30%. The total amount of image data, in this case 300 Mbyte, which has to be transmitted via the network is reduced by a factor of two, and the required network bandwidth is reduced similarly",

author = "Klotchkov, {I. V.} and Steen Pedersen",

note = "Copyright: 1996 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE; 1996 IEEE Symposium and Workshop on Engineering of Computer-Based Systems, ECBS 1996 ; Conference date: 11-03-1996 Through 15-03-1996",

year = "1996",

doi = "10.1109/ECBS.1996.494565",

language = "English",

isbn = "08-18-67355-9",

pages = "389--394",

booktitle = "Proceedings of the IEEE Symposium and Workshop on Engineering of Computer-Based Systems",

publisher = "IEEE",

address = "United States",

url = "https://ieeexplore.ieee.org/xpl/conhome/3565/proceeding",

}

Klotchkov, IV & Pedersen, S 1996, A codesign case study: implementing arithmetic functions in FPGAs. in Proceedings of the IEEE Symposium and Workshop on Engineering of Computer-Based Systems. IEEE, pp. 389-394, 1996 IEEE Symposium and Workshop on Engineering of Computer-Based Systems, Friedrichshafen, Baden-Württemberg, Germany, 11/03/1996. https://doi.org/10.1109/ECBS.1996.494565

TY - GEN

T1 - A codesign case study: implementing arithmetic functions in FPGAs

AU - Klotchkov, I. V.

AU - Pedersen, Steen

N1 - Copyright: 1996 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE

PY - 1996

Y1 - 1996

N2 - Different ways of implementing and designing arithmetic functions for 16/32 bit integers in FPGA technology are studied. A comparison of four different design methods is also included. The results are used to increase the overall system performance in a dedicated 3D image analysis prototype system by moving a vector length calculation from software to hardware. The conclusion is that by adding one relatively simple board containing two FPGAs in the prototype setup, the total computing time is reduced by 30%. The total amount of image data, in this case 300 Mbyte, which has to be transmitted via the network is reduced by a factor of two, and the required network bandwidth is reduced similarly

AB - Different ways of implementing and designing arithmetic functions for 16/32 bit integers in FPGA technology are studied. A comparison of four different design methods is also included. The results are used to increase the overall system performance in a dedicated 3D image analysis prototype system by moving a vector length calculation from software to hardware. The conclusion is that by adding one relatively simple board containing two FPGAs in the prototype setup, the total computing time is reduced by 30%. The total amount of image data, in this case 300 Mbyte, which has to be transmitted via the network is reduced by a factor of two, and the required network bandwidth is reduced similarly

U2 - 10.1109/ECBS.1996.494565

DO - 10.1109/ECBS.1996.494565

M3 - Article in proceedings

SN - 08-18-67355-9

SP - 389

EP - 394

BT - Proceedings of the IEEE Symposium and Workshop on Engineering of Computer-Based Systems

PB - IEEE

T2 - 1996 IEEE Symposium and Workshop on Engineering of Computer-Based Systems

Y2 - 11 March 1996 through 15 March 1996

ER -

A codesign case study: implementing arithmetic functions in FPGAs

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