## Abstract

Different ways of implementing and designing arithmetic functions for 16/32 bit integers in FPGA technology are studied. A comparison of four different design methods is also included. The results are used to increase the overall system performance in a dedicated 3D image analysis prototype system by moving a vector length calculation from software to hardware. The conclusion is that by adding one relatively simple board containing two FPGAs in the prototype setup, the total computing time is reduced by 30%. The total amount of image data, in this case 300 Mbyte, which has to be transmitted via the network is reduced by a factor of two, and the required network bandwidth is reduced similarly

Original language | English |
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Title of host publication | Proceedings of the IEEE Symposium and Workshop on Engineering of Computer-Based Systems |

Publisher | IEEE |

Publication date | 1996 |

Pages | 389-394 |

ISBN (Print) | 08-18-67355-9 |

DOIs | |

Publication status | Published - 1996 |

Event | 1996 IEEE Symposium and Workshop on Engineering of Computer-Based Systems - Friedrichshafen, Germany Duration: 11 Mar 1996 → 15 Mar 1996 https://ieeexplore.ieee.org/xpl/conhome/3565/proceeding |

### Conference

Conference | 1996 IEEE Symposium and Workshop on Engineering of Computer-Based Systems |
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Country/Territory | Germany |

City | Friedrichshafen |

Period | 11/03/1996 → 15/03/1996 |

Internet address |