A codesign case study: implementing arithmetic functions in FPGAs

I. V. Klotchkov, Steen Pedersen

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    Abstract

    Different ways of implementing and designing arithmetic functions for 16/32 bit integers in FPGA technology are studied. A comparison of four different design methods is also included. The results are used to increase the overall system performance in a dedicated 3D image analysis prototype system by moving a vector length calculation from software to hardware. The conclusion is that by adding one relatively simple board containing two FPGAs in the prototype setup, the total computing time is reduced by 30%. The total amount of image data, in this case 300 Mbyte, which has to be transmitted via the network is reduced by a factor of two, and the required network bandwidth is reduced similarly
    Original languageEnglish
    Title of host publicationProceedings of the IEEE Symposium and Workshop on Engineering of Computer-Based Systems
    PublisherIEEE
    Publication date1996
    Pages389-394
    ISBN (Print)08-18-67355-9
    DOIs
    Publication statusPublished - 1996
    EventIEEE Symposium and Workshop on Engineering of Computer-Based Systems - Friedrichshafen
    Duration: 1 Jan 1996 → …

    Conference

    ConferenceIEEE Symposium and Workshop on Engineering of Computer-Based Systems
    CityFriedrichshafen
    Period01/01/1996 → …

    Bibliographical note

    Copyright: 1996 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE

    Cite this

    Klotchkov, I. V., & Pedersen, S. (1996). A codesign case study: implementing arithmetic functions in FPGAs. In Proceedings of the IEEE Symposium and Workshop on Engineering of Computer-Based Systems (pp. 389-394). IEEE. https://doi.org/10.1109/ECBS.1996.494565