A Capacitor-Free, Fast Transient Response Linear Voltage Regulator In a 180nm CMOS

Alexander N. Deleuran; Nicklas Lindbjerg; Martin K.  Pedersen; Pere Llimos Muntal; Ivan Harald Holger Jørgensen

doi:10.1109/NORCHIP.2015.7364358

A Capacitor-Free, Fast Transient Response Linear Voltage Regulator In a 180nm CMOS

Alexander N. Deleuran, Nicklas Lindbjerg, Martin K. Pedersen, Pere Llimos Muntal, Ivan Harald Holger Jørgensen

Research output: Chapter in Book/Report/Conference proceeding › Article in proceedings › Research › peer-review

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Abstract

A 1.8 V capacitor-free linear regulator with fast transient response based on a new topology with a fast and slow regulation loop is presented. The design has been laid out and simulated in a 0.18 µm CMOS process. The design has a low component count and is tailored for system-on-chip integration. A current step load from 0-50 mA with a rise time of 1 µs results in an undershoot in the output voltage of 140 mV for a period of 39 ns. The regulator sources up to 50 mA current load.

Original language	English
Title of host publication	Proceedings of NORCAS 2015
Number of pages	4
Publisher	IEEE
Publication date	2015
ISBN (Print)	978-1-4673-6576-5
DOIs	https://doi.org/10.1109/NORCHIP.2015.7364358
Publication status	Published - 2015
Event	1st IEEE Nordic Circuits and Systems Conference (NORCAS 2015) - Oslo, Norway Duration: 26 Oct 2015 → 28 Oct 2015 Conference number: 1 http://www.norcas.org/

Conference

Conference	1st IEEE Nordic Circuits and Systems Conference (NORCAS 2015)
Number	1
Country	Norway
City	Oslo
Period	26/10/2015 → 28/10/2015
Other	A merge of NORCHIP and the International Symposium on System-on-Chip (SoC)
Internet address	http://www.norcas.org/

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10.1109/NORCHIP.2015.7364358

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Cite this

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title = "A Capacitor-Free, Fast Transient Response Linear Voltage Regulator In a 180nm CMOS",

abstract = "A 1.8 V capacitor-free linear regulator with fast transient response based on a new topology with a fast and slow regulation loop is presented. The design has been laid out and simulated in a 0.18 µm CMOS process. The design has a low component count and is tailored for system-on-chip integration. A current step load from 0-50 mA with a rise time of 1 µs results in an undershoot in the output voltage of 140 mV for a period of 39 ns. The regulator sources up to 50 mA current load.",

author = "Deleuran, {Alexander N.} and Nicklas Lindbjerg and Pedersen, {Martin K.} and {Llimos Muntal}, Pere and J{\o}rgensen, {Ivan Harald Holger}",

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language = "English",

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AU - Lindbjerg, Nicklas

AU - Pedersen, Martin K.

AU - Llimos Muntal, Pere

AU - Jørgensen, Ivan Harald Holger

N1 - Conference code: 1

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N2 - A 1.8 V capacitor-free linear regulator with fast transient response based on a new topology with a fast and slow regulation loop is presented. The design has been laid out and simulated in a 0.18 µm CMOS process. The design has a low component count and is tailored for system-on-chip integration. A current step load from 0-50 mA with a rise time of 1 µs results in an undershoot in the output voltage of 140 mV for a period of 39 ns. The regulator sources up to 50 mA current load.

AB - A 1.8 V capacitor-free linear regulator with fast transient response based on a new topology with a fast and slow regulation loop is presented. The design has been laid out and simulated in a 0.18 µm CMOS process. The design has a low component count and is tailored for system-on-chip integration. A current step load from 0-50 mA with a rise time of 1 µs results in an undershoot in the output voltage of 140 mV for a period of 39 ns. The regulator sources up to 50 mA current load.

U2 - 10.1109/NORCHIP.2015.7364358

DO - 10.1109/NORCHIP.2015.7364358

M3 - Article in proceedings

SN - 978-1-4673-6576-5

BT - Proceedings of NORCAS 2015

PB - IEEE

T2 - 1st IEEE Nordic Circuits and Systems Conference (NORCAS 2015)

Y2 - 26 October 2015 through 28 October 2015

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