A novel method to calibrate the frequency response of a Phase-Locked Loop is presented. The method requires just an additional digital counter and an auxiliary Phase-Frequency Detector (PFD) to measure the natural frequency of the PLL. The measured value can be used to tune the PLL response to the desired value. The method is demonstrated mathematically on a typical PLL topology and it is extended to ΣΔ fractional-N PLLs. A set of simulations performed with two different simulators is used to verify the applicability of the method.
|Title of host publication||Proceedings IEEE International Symposium on Circuits and Systems|
|Publication status||Published - 2004|
|Event||2004 IEEE International Symposium on Circuits and Systems - Vancouver, Canada|
Duration: 23 May 2004 → 26 May 2004
|Conference||2004 IEEE International Symposium on Circuits and Systems|
|Period||23/05/2004 → 26/05/2004|