A calibration method for PLLs based on transient response

Marco Cassia, Peter Jivan Shah, Erik Bruun

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    Abstract

    A novel method to calibrate the frequency response of a Phase-Locked Loop is presented. The method requires just an additional digital counter and an auxiliary Phase-Frequency Detector (PFD) to measure the natural frequency of the PLL. The measured value can be used to tune the PLL response to the desired value. The method is demonstrated mathematically on a typical PLL topology and it is extended to ΣΔ fractional-N PLLs. A set of simulations performed with two different simulators is used to verify the applicability of the method.
    Original languageEnglish
    Title of host publicationProceedings IEEE International Symposium on Circuits and Systems
    Volume4
    PublisherIEEE
    Publication date2004
    Pages481-484
    ISBN (Print)0-7803-8251-X
    Publication statusPublished - 2004
    Event2004 IEEE International Symposium on Circuits and Systems - Vancouver, Canada
    Duration: 23 May 200426 May 2004
    http://www.cmsworldwide.com/ISCAS2004/

    Conference

    Conference2004 IEEE International Symposium on Circuits and Systems
    Country/TerritoryCanada
    CityVancouver
    Period23/05/200426/05/2004
    Internet address

    Bibliographical note

    Copyright: 2004 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE

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