This paper presents a complete design tool which performs automatic behavioral synthesis of asynchronous circuits (resource sharing, scheduling and binding). The tool targets a traditional control-datapath-style template architecture. Within the limitations set by this template architecture it is possible to optimize for area (which is our main focus) or for speed. This is done by simply using different cost functions. Input to the tool is a behavioral description in the Haste language, and output from the tool is a Haste program escribing the synthesized implementation consisting of a datapath and a controller. The tool may be seen as an add-on to the Haste/TiDE tool flow, and it can be used to automatically optimize parts of a design and to quickly xplore alternative optimizations. The paper outlines the design flow, explains key elements of the design tool, and presents a number of benchmark results.
|Title of host publication||Proceedings of the 15th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'09)|
|Publisher||IEEE Computer Society Press|
|Publication status||Published - 2009|
|Event||15th IEEE International Symposium on Asynchronous Circuits and Systems - |
Duration: 1 Jan 2009 → …
|Conference||15th IEEE International Symposium on Asynchronous Circuits and Systems|
|Period||01/01/2009 → …|