A 65-nm CMOS Area Optimized
De-synchronization Flow for sub-VT Designs

Christoph Müller; Steffen Malkowsky; Oskar Andersson; Babak Mohammadi; Jens Sparsø; Joachim Rodrigues

doi:10.1109/VLSI-SoC.2013.6673313

A 65-nm CMOS Area Optimized De-synchronization Flow for sub-V_T Designs

Christoph Müller, Steffen Malkowsky, Oskar Andersson, Babak Mohammadi, Jens Sparsø, Joachim Rodrigues

Lund University

Research output: Chapter in Book/Report/Conference proceeding › Article in proceedings › Research › peer-review

Abstract

This paper proposes a process independent post layout de-synchronization flow implemented in tool command language working on designs operating in the sub-VT regime. The overhead due to the self-timed operation is combated by introducing full-custom delay elements and latches for a standard 65-nm CMOS process. The flow offers the possibility to adjust granularity based on user requirements. Case studies with different reference designs manifested an average reduction of area and power overhead from 105% to 9% and 174% to 58% in comparison to a full standard cell de-synchronization approach.

Original language	English
Title of host publication	2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration (VLSI-SoC)
Publisher	IEEE
Publication date	2013
Pages	380-385
DOIs	https://doi.org/10.1109/VLSI-SoC.2013.6673313
Publication status	Published - 2013
Event	21st IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC) - Istanbul, Turkey Duration: 7 Oct 2013 → 9 Oct 2013 http://vlsisoc2013.ozyegin.edu.tr/

Conference

Conference	21st IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)
Country/Territory	Turkey
City	Istanbul
Period	07/10/2013 → 09/10/2013
Internet address	http://vlsisoc2013.ozyegin.edu.tr/

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10.1109/VLSI-SoC.2013.6673313

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Cite this

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title = "A 65-nm CMOS Area Optimized De-synchronization Flow for sub-VT Designs",

abstract = "This paper proposes a process independent post layout de-synchronization flow implemented in tool command language working on designs operating in the sub-VT regime. The overhead due to the self-timed operation is combated by introducing full-custom delay elements and latches for a standard 65-nm CMOS process. The flow offers the possibility to adjust granularity based on user requirements. Case studies with different reference designs manifested an average reduction of area and power overhead from 105% to 9% and 174% to 58% in comparison to a full standard cell de-synchronization approach.",

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pages = "380--385",

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publisher = "IEEE",

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note = "21st IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC) ; Conference date: 07-10-2013 Through 09-10-2013",

url = "http://vlsisoc2013.ozyegin.edu.tr/",

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Müller, C, Malkowsky, S, Andersson, O, Mohammadi, B, Sparsø, J & Rodrigues, J 2013, A 65-nm CMOS Area Optimized De-synchronization Flow for sub-V_T Designs. in 2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration (VLSI-SoC). IEEE, pp. 380-385, 21st IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), Istanbul, Turkey, 07/10/2013. https://doi.org/10.1109/VLSI-SoC.2013.6673313

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