A 65-nm CMOS Area Optimized De-synchronization Flow for sub-VT Designs

Christoph Müller, Steffen Malkowsky, Oskar Andersson, Babak Mohammadi, Jens Sparsø, Joachim Rodrigues

Research output: Chapter in Book/Report/Conference proceedingArticle in proceedingsResearchpeer-review

Abstract

This paper proposes a process independent post layout de-synchronization flow implemented in tool command language working on designs operating in the sub-VT regime. The overhead due to the self-timed operation is combated by introducing full-custom delay elements and latches for a standard 65-nm CMOS process. The flow offers the possibility to adjust granularity based on user requirements. Case studies with different reference designs manifested an average reduction of area and power overhead from 105% to 9% and 174% to 58% in comparison to a full standard cell de-synchronization approach.
Original languageEnglish
Title of host publication2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration (VLSI-SoC)
PublisherIEEE
Publication date2013
Pages380-385
DOIs
Publication statusPublished - 2013
Event21st IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC) - Istanbul, Turkey
Duration: 7 Oct 20139 Oct 2013
http://vlsisoc2013.ozyegin.edu.tr/

Conference

Conference21st IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)
CountryTurkey
CityIstanbul
Period07/10/201309/10/2013
Internet address

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