A 2.5 gb/s GaAs ATM Mux Demux ASIC

Jens Kargaard Madsen, Peter Stuhr Lassen

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    This paper describes the design and implementation of a high speed GaAs ATM Mux Demur ASIC (AMDA) which is the key element in a high speed ATM Add-Drop unit. This unit is used in a new distributed ATM multiplexing-demultiplexing architecture for broadband switching systems. The Add-Drop unit provides a cell based interface between networks/systems operating at different data rates, the high speed interface being 2.5 Gb/s and the low speed interface being 155/622 Mb/s. Self-timed FIFOs are used for handling the speed gaps between domains operating at different clock rates, and a Self-Timed At Receiver's Input (STARI) interface is used at all high speed chip-to-chip links to eliminate timing skews The AMDA demonstrated operation above 4 Gb/s (500 MHz clock frequency) with an associated power dissipation of 5 W
    Original languageEnglish
    Title of host publicationTechnical Digest of the 17th Annual IEEE Gallium Arsenide Integrated Circuit Symposium
    Publication date1995
    ISBN (Print)07-80-32966-X
    Publication statusPublished - 1995
    Event17th Annual IEEE Gallium Arsenide Integrated Circuit Symposium - San Diego, CA, United States
    Duration: 28 Oct 19951 Nov 1995
    Conference number: 17


    Conference17th Annual IEEE Gallium Arsenide Integrated Circuit Symposium
    Country/TerritoryUnited States
    CitySan Diego, CA
    Internet address

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    Copyright: 1995 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE


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