A 10-bit 100 MSamples/s BiCMOS D/A Converter

Ivan Harald Holger Jørgensen; Svein Anders Tunheim

doi:10.1109/ISCAS.1996.539975

A 10-bit 100 MSamples/s BiCMOS D/A Converter

Ivan Harald Holger Jørgensen
, Svein Anders Tunheim

SINTEF

Research output: Chapter in Book/Report/Conference proceeding › Article in proceedings › Research › peer-review

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Abstract

A 10-bit 100 MSamples/s current-steering D/A converter (DAC) has been designed and processed in a 0.8 μm BiCMOS process. The DAC is intended for applications using direct digital synthesis, and focus has been set on reducing dynamic nonlinearities to achieve a high spurious free dynamic range (SFDR1) at high generated frequencies. The main part of the DAC consists of a matrix of current cells. Each current cell contains an emitter-coupled logic (ECL) flip-flop, clocked by a global ECL clock to ensure accurate clocking. A bipolar differential pair, steered by the differential output of the ECL flip-flop, is used in each current cell to steer the current. The DAC operates at 5 V, and has a power consumption of 650 mW. The area of the chip-core is 2.2 mm×2.2 mm. The measured integral nonlinearity (INL) and differential nonlinearity (DNL) were both approximately 2 LSB. At a generated frequency of fg≈0.3·fs (fs=100 MSamples/s), the measured SFDR was approximately 43 dB

Original language	English
Title of host publication	Proc. 1996 IEEE International Symposium on Circuits and Systems
Place of Publication	Piscataway
Publisher	IEEE
Publication date	1996
Pages	425-428
ISBN (Print)	0-7803-3073-0
DOIs	https://doi.org/10.1109/ISCAS.1996.539975
Publication status	Published - 1996
Event	1996 IEEE International Symposium on Circuits and Systems - Atlanta, GA, United States Duration: 12 May 1996 → 15 May 1996 http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=3834

Conference

Conference	1996 IEEE International Symposium on Circuits and Systems
Country/Territory	United States
City	Atlanta, GA
Period	12/05/1996 → 15/05/1996
Internet address	http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=3834

Bibliographical note

Copyright: 1996 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE

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@inproceedings{e000f2d46e6d4a12b5cc1d0c65360bd7,

title = "A 10-bit 100 MSamples/s BiCMOS D/A Converter",

abstract = "A 10-bit 100 MSamples/s current-steering D/A converter (DAC) has been designed and processed in a 0.8 μm BiCMOS process. The DAC is intended for applications using direct digital synthesis, and focus has been set on reducing dynamic nonlinearities to achieve a high spurious free dynamic range (SFDR1) at high generated frequencies. The main part of the DAC consists of a matrix of current cells. Each current cell contains an emitter-coupled logic (ECL) flip-flop, clocked by a global ECL clock to ensure accurate clocking. A bipolar differential pair, steered by the differential output of the ECL flip-flop, is used in each current cell to steer the current. The DAC operates at 5 V, and has a power consumption of 650 mW. The area of the chip-core is 2.2 mm{\texttimes}2.2 mm. The measured integral nonlinearity (INL) and differential nonlinearity (DNL) were both approximately 2 LSB. At a generated frequency of fg\≈0.3·fs (fs=100 MSamples/s), the measured SFDR was approximately 43 dB",

author = "J{\o}rgensen, \{Ivan Harald Holger\} and Tunheim, \{Svein Anders\}",

note = "Copyright: 1996 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE; 1996 IEEE International Symposium on Circuits and Systems, ISCAS'96 ; Conference date: 12-05-1996 Through 15-05-1996",

year = "1996",

doi = "10.1109/ISCAS.1996.539975",

language = "English",

isbn = "0-7803-3073-0",

pages = "425--428",

booktitle = "Proc. 1996 IEEE International Symposium on Circuits and Systems",

publisher = "IEEE",

address = "United States",

url = "http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=3834",

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T1 - A 10-bit 100 MSamples/s BiCMOS D/A Converter

AU - Jørgensen, Ivan Harald Holger

AU - Tunheim, Svein Anders

N1 - Copyright: 1996 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE

PY - 1996

Y1 - 1996

N2 - A 10-bit 100 MSamples/s current-steering D/A converter (DAC) has been designed and processed in a 0.8 μm BiCMOS process. The DAC is intended for applications using direct digital synthesis, and focus has been set on reducing dynamic nonlinearities to achieve a high spurious free dynamic range (SFDR1) at high generated frequencies. The main part of the DAC consists of a matrix of current cells. Each current cell contains an emitter-coupled logic (ECL) flip-flop, clocked by a global ECL clock to ensure accurate clocking. A bipolar differential pair, steered by the differential output of the ECL flip-flop, is used in each current cell to steer the current. The DAC operates at 5 V, and has a power consumption of 650 mW. The area of the chip-core is 2.2 mm×2.2 mm. The measured integral nonlinearity (INL) and differential nonlinearity (DNL) were both approximately 2 LSB. At a generated frequency of fg≈0.3·fs (fs=100 MSamples/s), the measured SFDR was approximately 43 dB

AB - A 10-bit 100 MSamples/s current-steering D/A converter (DAC) has been designed and processed in a 0.8 μm BiCMOS process. The DAC is intended for applications using direct digital synthesis, and focus has been set on reducing dynamic nonlinearities to achieve a high spurious free dynamic range (SFDR1) at high generated frequencies. The main part of the DAC consists of a matrix of current cells. Each current cell contains an emitter-coupled logic (ECL) flip-flop, clocked by a global ECL clock to ensure accurate clocking. A bipolar differential pair, steered by the differential output of the ECL flip-flop, is used in each current cell to steer the current. The DAC operates at 5 V, and has a power consumption of 650 mW. The area of the chip-core is 2.2 mm×2.2 mm. The measured integral nonlinearity (INL) and differential nonlinearity (DNL) were both approximately 2 LSB. At a generated frequency of fg≈0.3·fs (fs=100 MSamples/s), the measured SFDR was approximately 43 dB

U2 - 10.1109/ISCAS.1996.539975

DO - 10.1109/ISCAS.1996.539975

M3 - Article in proceedings

SN - 0-7803-3073-0

SP - 425

EP - 428

BT - Proc. 1996 IEEE International Symposium on Circuits and Systems

PB - IEEE

CY - Piscataway

T2 - 1996 IEEE International Symposium on Circuits and Systems

Y2 - 12 May 1996 through 15 May 1996

ER -

A 10-bit 100 MSamples/s BiCMOS D/A Converter

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