A 10-bit 100 MSamples/s BiCMOS D/A Converter

Ivan Harald Holger Jørgensen, Svein Anders Tunheim

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    A 10-bit 100 MSamples/s current-steering D/A converter (DAC) has been designed and processed in a 0.8 μm BiCMOS process. The DAC is intended for applications using direct digital synthesis, and focus has been set on reducing dynamic nonlinearities to achieve a high spurious free dynamic range (SFDR1) at high generated frequencies. The main part of the DAC consists of a matrix of current cells. Each current cell contains an emitter-coupled logic (ECL) flip-flop, clocked by a global ECL clock to ensure accurate clocking. A bipolar differential pair, steered by the differential output of the ECL flip-flop, is used in each current cell to steer the current. The DAC operates at 5 V, and has a power consumption of 650 mW. The area of the chip-core is 2.2 mm×2.2 mm. The measured integral nonlinearity (INL) and differential nonlinearity (DNL) were both approximately 2 LSB. At a generated frequency of fg≈0.3·fs (fs=100 MSamples/s), the measured SFDR was approximately 43 dB
    Original languageEnglish
    Title of host publicationProc. 1996 IEEE International Symposium on Circuits and Systems
    Place of PublicationPiscataway
    Publication date1996
    ISBN (Print)0-7803-3073-0
    Publication statusPublished - 1996
    Event1996 IEEE International Symposium on Circuits and Systems - Atlanta, GA, United States
    Duration: 12 May 199615 May 1996


    Conference1996 IEEE International Symposium on Circuits and Systems
    Country/TerritoryUnited States
    CityAtlanta, GA
    Internet address

    Bibliographical note

    Copyright: 1996 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE


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