A 0.2 V 0.44 µW 20 kHz Analog to Digital Σ∆ Modulator with 57 fJ/conversion FoM

Ulrik Sørensen Wismar, Dag Wisland, Pietro Andreani

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    This paper presents a 90 nm CMOS ΣΔ A/D modulator operating with a supply voltage of 0.2 V, well below the threshold voltage of the transistors. The modulator is an open-loop first-order architecture based on a frequency-modulated intermediate signal, generated in a ring voltage-controlled oscillator. The linearity of the modulator is greatly improved by the adoption of a so-called soft-rail in the oscillator. Measurements show a dynamic range of 52 dB over a 20 kHz signal bandwidth with a sampling frequency of 3.4 MHz, for a total power consumption as low as 0.44 μW. The corresponding peak SNDR is 44.2 dB, while the peak SNR is 47.4 dB.
    Original languageEnglish
    Title of host publicationProceedings of the 32nd European Solid-State Circuits Conference, 2006. ESSCIRC 2006.
    Publication date2006
    ISBN (Print)1-4244-0303-0
    Publication statusPublished - 2006
    EventThe 32nd European Solid-State Circuits Conference - Montreux, Switzerland
    Duration: 18 Sep 200622 Sep 2006


    ConferenceThe 32nd European Solid-State Circuits Conference

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