A 0.2 V 0.44 µW 20 kHz Analog to Digital Σ∆  Modulator with 57 fJ/conversion FoM

Ulrik Sørensen Wismar; Dag Wisland; Pietro Andreani

doi:10.1109/ESSCIR.2006.307562

A 0.2 V 0.44 µW 20 kHz Analog to Digital Σ∆ Modulator with 57 fJ/conversion FoM

Ulrik Sørensen Wismar, Dag Wisland, Pietro Andreani

Research output: Chapter in Book/Report/Conference proceeding › Article in proceedings › Research › peer-review

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Abstract

This paper presents a 90 nm CMOS ΣΔ A/D modulator operating with a supply voltage of 0.2 V, well below the threshold voltage of the transistors. The modulator is an open-loop first-order architecture based on a frequency-modulated intermediate signal, generated in a ring voltage-controlled oscillator. The linearity of the modulator is greatly improved by the adoption of a so-called soft-rail in the oscillator. Measurements show a dynamic range of 52 dB over a 20 kHz signal bandwidth with a sampling frequency of 3.4 MHz, for a total power consumption as low as 0.44 μW. The corresponding peak SNDR is 44.2 dB, while the peak SNR is 47.4 dB.

Original language	English
Title of host publication	Proceedings of the 32nd European Solid-State Circuits Conference, 2006. ESSCIRC 2006.
Publisher	IEEE
Publication date	2006
ISBN (Print)	1-4244-0303-0
DOIs	https://doi.org/10.1109/ESSCIR.2006.307562
Publication status	Published - 2006
Event	The 32nd European Solid-State Circuits Conference - Montreux, Switzerland Duration: 18 Sept 2006 → 22 Sept 2006

Conference

Conference	The 32nd European Solid-State Circuits Conference
Country/Territory	Switzerland
City	Montreux
Period	18/09/2006 → 22/09/2006

Bibliographical note

Copyright: 2006 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE

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10.1109/ESSCIR.2006.307562

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Cite this

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title = "A 0.2 V 0.44 µW 20 kHz Analog to Digital Σ∆ Modulator with 57 fJ/conversion FoM",

abstract = "This paper presents a 90 nm CMOS ΣΔ A/D modulator operating with a supply voltage of 0.2 V, well below the threshold voltage of the transistors. The modulator is an open-loop first-order architecture based on a frequency-modulated intermediate signal, generated in a ring voltage-controlled oscillator. The linearity of the modulator is greatly improved by the adoption of a so-called soft-rail in the oscillator. Measurements show a dynamic range of 52 dB over a 20 kHz signal bandwidth with a sampling frequency of 3.4 MHz, for a total power consumption as low as 0.44 μW. The corresponding peak SNDR is 44.2 dB, while the peak SNR is 47.4 dB.",

author = "Wismar, {Ulrik S{\o}rensen} and Dag Wisland and Pietro Andreani",

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N1 - Copyright: 2006 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE

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N2 - This paper presents a 90 nm CMOS ΣΔ A/D modulator operating with a supply voltage of 0.2 V, well below the threshold voltage of the transistors. The modulator is an open-loop first-order architecture based on a frequency-modulated intermediate signal, generated in a ring voltage-controlled oscillator. The linearity of the modulator is greatly improved by the adoption of a so-called soft-rail in the oscillator. Measurements show a dynamic range of 52 dB over a 20 kHz signal bandwidth with a sampling frequency of 3.4 MHz, for a total power consumption as low as 0.44 μW. The corresponding peak SNDR is 44.2 dB, while the peak SNR is 47.4 dB.

AB - This paper presents a 90 nm CMOS ΣΔ A/D modulator operating with a supply voltage of 0.2 V, well below the threshold voltage of the transistors. The modulator is an open-loop first-order architecture based on a frequency-modulated intermediate signal, generated in a ring voltage-controlled oscillator. The linearity of the modulator is greatly improved by the adoption of a so-called soft-rail in the oscillator. Measurements show a dynamic range of 52 dB over a 20 kHz signal bandwidth with a sampling frequency of 3.4 MHz, for a total power consumption as low as 0.44 μW. The corresponding peak SNDR is 44.2 dB, while the peak SNR is 47.4 dB.

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DO - 10.1109/ESSCIR.2006.307562

M3 - Article in proceedings

SN - 1-4244-0303-0

BT - Proceedings of the 32nd European Solid-State Circuits Conference, 2006. ESSCIRC 2006.

PB - IEEE

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