5.8 Gb/s 16:1 multiplexer and 1:16 demultiplexer using 1.2 μm BiCMOS

Jacob Midtgaard, C. Svensson

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    Abstract

    High speed time-division multiplexers and demultiplexers are important components of modern optical communication systems. They are needed to parallelize the data to allow most of the system to operate at much lower speeds. This paper describes a 16:1 multiplexer and a 1:16 demultiplexer implemented on one IC in a 1.2 μm BiCMOS process. The IC combines fast ECL circuits with CMOS circuits, demonstrating that by utilizing the combination of bipolar and MOS transistors, a VLSI circuit with very high speed interface is feasible
    Original languageEnglish
    Title of host publicationProceedings of the IEEE International Symposium on Circuits and Systems
    VolumeVolume 4
    PublisherIEEE
    Publication date1994
    Pages43-46
    ISBN (Print)07-80-31915-X
    DOIs
    Publication statusPublished - 1994
    Event1994 IEEE International Symposium on Circuits and Systems - London, United Kingdom
    Duration: 30 May 19942 Jun 1994
    http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=3224

    Conference

    Conference1994 IEEE International Symposium on Circuits and Systems
    CountryUnited Kingdom
    CityLondon
    Period30/05/199402/06/1994
    Internet address

    Bibliographical note

    Copyright 1994 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.

    Cite this

    Midtgaard, J., & Svensson, C. (1994). 5.8 Gb/s 16:1 multiplexer and 1:16 demultiplexer using 1.2 μm BiCMOS. In Proceedings of the IEEE International Symposium on Circuits and Systems (Vol. Volume 4, pp. 43-46). IEEE. https://doi.org/10.1109/ISCAS.1994.409192