34.3 fJ/conv.-step 8-MHz Bandwidth Fourth-Order Pseudo-Differential Ring-Amplifier-Based Continuous-Time Delta–Sigma ADC in 65 nm

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This letter presents two pseudo-differential ring amplifiers (RAs) suitable for a continuous-time (CT) operation as an alternative to traditional amplifiers. The designs retain the advantages of RAs, scale with process technology, and do not require a periodic reset. The RAs are designed to operate in an integrator configuration and use different methods to achieve stability in continuous time. A prototype was fabricated in a 65-nm CMOS containing two versions of a CT delta–sigma ADC using the two RAs presented. The ADCs consist of a fourth-order loop filter with optimized zeros, a single-bit quantizer that operates at a sampling frequency of 320 MHz, and a digital-to-analog converter. The best design proposed achieves a measured peak signal-to-noise and distortion ratio of 50.6 dB for an 8-MHz bandwidth, a dynamic range of 53.2 dB, and consumes 152 ${\mu }\text{W}$ at a supply of 1.1 V. The obtained figure of merit is 34.3 fJ/conv.-step which outperforms state-of-the-art delta–sigma ADCs in that specification range and is 77% superior to its traditional operational transconductance amplifier-based ADC counterpart.
Original languageEnglish
JournalIeee Solid-state Circuits Letters
Issue number10
Pages (from-to)198-201
Publication statusPublished - 2018
CitationsWeb of Science® Times Cited: No match on DOI

    Research areas

  • Analog to digital converter, Continuous-time (CT), Delta–sigma, Oversampled, Ring amplifiers (RAs)

ID: 176486136