# 34.3 fJ/conv.-step 8-MHz Bandwidth Fourth-Order Pseudo-Differential Ring-Amplifier-Based Continuous-Time Delta–Sigma ADC in 65 nm

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### Abstract

This letter presents two pseudo-differential ring amplifiers (RAs) suitable for a continuous-time (CT) operation as an alternative to traditional amplifiers. The designs retain the advantages of RAs, scale with process technology, and do not require a periodic reset. The RAs are designed to operate in an integrator configuration and use different methods to achieve stability in continuous time. A prototype was fabricated in a 65-nm CMOS containing two versions of a CT delta–sigma ADC using the two RAs presented. The ADCs consist of a fourth-order loop filter with optimized zeros, a single-bit quantizer that operates at a sampling frequency of 320 MHz, and a digital-to-analog converter. The best design proposed achieves a measured peak signal-to-noise and distortion ratio of 50.6 dB for an 8-MHz bandwidth, a dynamic range of 53.2 dB, and consumes 152 ${\mu }\text{W}$ at a supply of 1.1 V. The obtained figure of merit is 34.3 fJ/conv.-step which outperforms state-of-the-art delta–sigma ADCs in that specification range and is 77% superior to its traditional operational transconductance amplifier-based ADC counterpart.
Original language English Ieee Solid-state Circuits Letters 1 10 198-201 2573-9603 https://doi.org/10.1109/LSSC.2019.2910468 Published - 2018

### Keywords

• Analog to digital converter
• Continuous-time (CT)
• Delta–sigma
• Oversampled
• Ring amplifiers (RAs)

### Cite this

@article{43d3f8ea2289479c91a6dd0297bdc69d,
title = "34.3 fJ/conv.-step 8-MHz Bandwidth Fourth-Order Pseudo-Differential Ring-Amplifier-Based Continuous-Time Delta–Sigma ADC in 65 nm",
abstract = "This letter presents two pseudo-differential ring amplifiers (RAs) suitable for a continuous-time (CT) operation as an alternative to traditional amplifiers. The designs retain the advantages of RAs, scale with process technology, and do not require a periodic reset. The RAs are designed to operate in an integrator configuration and use different methods to achieve stability in continuous time. A prototype was fabricated in a 65-nm CMOS containing two versions of a CT delta–sigma ADC using the two RAs presented. The ADCs consist of a fourth-order loop filter with optimized zeros, a single-bit quantizer that operates at a sampling frequency of 320 MHz, and a digital-to-analog converter. The best design proposed achieves a measured peak signal-to-noise and distortion ratio of 50.6 dB for an 8-MHz bandwidth, a dynamic range of 53.2 dB, and consumes 152 ${\mu }\text{W}$ at a supply of 1.1 V. The obtained figure of merit is 34.3 fJ/conv.-step which outperforms state-of-the-art delta–sigma ADCs in that specification range and is 77{\%} superior to its traditional operational transconductance amplifier-based ADC counterpart.",
keywords = "Analog to digital converter, Continuous-time (CT), Delta–sigma, Oversampled, Ring amplifiers (RAs)",
author = "{Llimos Muntal}, Pere and J{\o}rgensen, {Ivan Harald Holger}",
year = "2018",
doi = "10.1109/LSSC.2019.2910468",
language = "English",
volume = "1",
pages = "198--201",
journal = "Ieee Solid-state Circuits Letters",
issn = "2573-9603",
number = "10",

}

In: Ieee Solid-state Circuits Letters, Vol. 1, No. 10, 2018, p. 198-201.

Research output: Contribution to journalJournal articleResearchpeer-review

TY - JOUR

T1 - 34.3 fJ/conv.-step 8-MHz Bandwidth Fourth-Order Pseudo-Differential Ring-Amplifier-Based Continuous-Time Delta–Sigma ADC in 65 nm

AU - Llimos Muntal, Pere

AU - Jørgensen, Ivan Harald Holger

PY - 2018

Y1 - 2018

N2 - This letter presents two pseudo-differential ring amplifiers (RAs) suitable for a continuous-time (CT) operation as an alternative to traditional amplifiers. The designs retain the advantages of RAs, scale with process technology, and do not require a periodic reset. The RAs are designed to operate in an integrator configuration and use different methods to achieve stability in continuous time. A prototype was fabricated in a 65-nm CMOS containing two versions of a CT delta–sigma ADC using the two RAs presented. The ADCs consist of a fourth-order loop filter with optimized zeros, a single-bit quantizer that operates at a sampling frequency of 320 MHz, and a digital-to-analog converter. The best design proposed achieves a measured peak signal-to-noise and distortion ratio of 50.6 dB for an 8-MHz bandwidth, a dynamic range of 53.2 dB, and consumes 152 ${\mu }\text{W}$ at a supply of 1.1 V. The obtained figure of merit is 34.3 fJ/conv.-step which outperforms state-of-the-art delta–sigma ADCs in that specification range and is 77% superior to its traditional operational transconductance amplifier-based ADC counterpart.

AB - This letter presents two pseudo-differential ring amplifiers (RAs) suitable for a continuous-time (CT) operation as an alternative to traditional amplifiers. The designs retain the advantages of RAs, scale with process technology, and do not require a periodic reset. The RAs are designed to operate in an integrator configuration and use different methods to achieve stability in continuous time. A prototype was fabricated in a 65-nm CMOS containing two versions of a CT delta–sigma ADC using the two RAs presented. The ADCs consist of a fourth-order loop filter with optimized zeros, a single-bit quantizer that operates at a sampling frequency of 320 MHz, and a digital-to-analog converter. The best design proposed achieves a measured peak signal-to-noise and distortion ratio of 50.6 dB for an 8-MHz bandwidth, a dynamic range of 53.2 dB, and consumes 152 ${\mu }\text{W}$ at a supply of 1.1 V. The obtained figure of merit is 34.3 fJ/conv.-step which outperforms state-of-the-art delta–sigma ADCs in that specification range and is 77% superior to its traditional operational transconductance amplifier-based ADC counterpart.

KW - Analog to digital converter

KW - Continuous-time (CT)

KW - Delta–sigma

KW - Oversampled

KW - Ring amplifiers (RAs)

U2 - 10.1109/LSSC.2019.2910468

DO - 10.1109/LSSC.2019.2910468

M3 - Journal article

VL - 1

SP - 198

EP - 201

JO - Ieee Solid-state Circuits Letters

JF - Ieee Solid-state Circuits Letters

SN - 2573-9603

IS - 10

ER -