34.3 fJ/conv.-step 8 MHz Bandwidth 4th-Order Pseudo-Differential Ring-Amplifier Based Continuous-Time Delta-Sigma ADC in 65 nm

This work presents two pseudo-differential ring amplifiers suitable for continuous-time operation as analternative to traditional amplifiers. The designs retain the advantages of ring amplifiers, scale with process technology and do not require a periodic reset. The ring amplifiers are designed to operate in an integrator configuration and they use different methods to achieve stability in continuous time. A prototype was fabricatedin 65 nm CMOS containing two versions of a continuous-time deltasigma ADC using the two ring amplifiers presented. The ADCs consist of a 4th-order loop filter with optimized zeros, a singlebit quantizer that operates at a sampling frequency of 320 MHz and a DAC. The best design proposed achieves a measured peak SNDR of 50.6 dB for an 8 MHz bandwidth, a DR of 53.2 dB and consumes 152 µW at a supply of 1.1 V. The obtained figure of merit is 34.3 fJ/conv.-step which outperforms state-of-the-art delta-sigma ADCs in that specification range and is 77% superior to its traditional OTA-based ADC counterpart.