The purpose of the project is to develop VHDL models of units for frame synchronization and Viterbi decoding to be used by the European Space Agency (ESA) for satellite communication at very high data rates (150 Mbit/s). The project was started with a study of algorithms and system architectures, and the first phase resulted in a number of suggestions for different units. Two of these were selected for a detailed design in the second phase: A Viterbi decoder for a data rate of 150 Mbit/s operating at half the clock rate (i.e. 75 MHz) and a frame synchronization unit to be placed after the Viterbi decoder. VHDL models for these two units were produced and the project is continued outside DTU with the actual manufacturing of the two units: an ASIC for the Viterbi decoder is made by VTT in Finland and an FPGA for the frame synchronizer unit is made by TERMA Elektronik A/S in Denmark.
|Effective start/end date||01/01/1995 → 31/10/1998|