Towards a Time-predictable Dual-Issue Microprocessor: The Patmos Approach

Publication: Research - peer-reviewArticle in proceedings – Annual report year: 2011

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Current processors are optimized for average case performance, often leading to a high worst-case execution time (WCET). Many architectural features that increase the average case performance are hard to be modeled for the WCET analysis. In this paper we present Patmos, a processor optimized for low WCET bounds rather than high average case performance. Patmos is a dualissue, statically scheduled RISC processor. The instruction cache is organized as a method cache and the data cache is organized as a split cache in order to simplify the cache WCET analysis. To fill the dual-issue pipeline with enough useful instructions, Patmos relies on a customized compiler. The compiler also plays a central role in optimizing the application for the WCET instead of average case performance.
Original languageEnglish
Title of host publicationBringing Theory to Practice: Predictability and Performance in Embedded Systems : PPES’11, March 18, 2011, Grenoble, France
Volume18
PublisherOASICS
Publication date2011
Pages11-21
ISBN (print)978-3-939897-28-6
DOIs
StatePublished

Conference

ConferenceWorkshop on Bringing Theory to Practice: Predictability and Performance in Embedded Systems
Number1
Period01/01/11 → …
CitationsWeb of Science® Times Cited: No match on DOI

Keywords

  • WCET analysis, WCET-aware compilation, Time-predictable architecture
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