Publication: Research - peer-review › Article in proceedings – Annual report year: 2011
Current processors are optimized for average case performance, often leading to a high worst-case execution time (WCET). Many architectural features that increase the average case performance are hard to be modeled for the WCET analysis. In this paper we present Patmos, a processor optimized for low WCET bounds rather than high average case performance. Patmos is a dualissue, statically scheduled RISC processor. The instruction cache is organized as a method cache and the data cache is organized as a split cache in order to simplify the cache WCET analysis. To fill the dual-issue pipeline with enough useful instructions, Patmos relies on a customized compiler. The compiler also plays a central role in optimizing the application for the WCET instead of average case performance.
|Title of host publication||Bringing Theory to Practice: Predictability and Performance in Embedded Systems : PPES’11, March 18, 2011, Grenoble, France|
|Conference||Workshop on Bringing Theory to Practice: Predictability and Performance in Embedded Systems|
|Period||01/01/11 → …|
|Citations||Web of Science® Times Cited: No match on DOI|
- WCET analysis, WCET-aware compilation, Time-predictable architecture
No data available