The ReNoC Reconfigurable Network-on-Chip : Architecture, Configuration Algorithms, and Evaluation

Publication: Research - peer-reviewJournal article – Annual report year: 2011

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This article presents a reconfigurable network-on-chip architecture called ReNoC, which is intended for use in general-purpose multiprocessor system-on-chip platforms, and which enables application-specific logical NoC topologies to be configured, thus providing both efficiency and flexibility. The article presents three novel algorithms that synthesize an application-specific NoC topology, map it onto the physical ReNoC architecture, and create deadlock-free, application-specific routing algorithms. We apply our algorithms to a mixture of real and synthetic applications and target three different physical architectures. Compared to a conventional NoC, ReNoC reduces power consumption by up to 58% on average.
Original languageEnglish
JournalA C M Transactions on Embedded Computing Systems
Publication date2011
Volume10
Journal number4
Pages45:1-45:26
ISSN1539-9087
DOIs
StatePublished
CitationsWeb of Science® Times Cited: 0

Keywords

  • Experimentation, Algorithms, System-on-chip, Mapping, Configuration, Routing, Performance, Synthesis, Network-on-chip
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