Techniques for Leakage Power Reduction in Nanoscale Circuits: A Survey

Publication: Research - peer-reviewReport – Annual report year: 2007

Standard

Techniques for Leakage Power Reduction in Nanoscale Circuits: A Survey. / Liu, Wei.

Informatics and Mathematical Modelling, Technical University of Denmark, DTU, 2007.

Publication: Research - peer-reviewReport – Annual report year: 2007

Harvard

Liu, W 2007, Techniques for Leakage Power Reduction in Nanoscale Circuits: A Survey. Informatics and Mathematical Modelling, Technical University of Denmark, DTU.

APA

Liu, W. (2007). Techniques for Leakage Power Reduction in Nanoscale Circuits: A Survey. Informatics and Mathematical Modelling, Technical University of Denmark, DTU.

CBE

Liu W 2007. Techniques for Leakage Power Reduction in Nanoscale Circuits: A Survey. Informatics and Mathematical Modelling, Technical University of Denmark, DTU.

MLA

Liu, Wei Techniques for Leakage Power Reduction in Nanoscale Circuits: A Survey Informatics and Mathematical Modelling, Technical University of Denmark, DTU. 2007.

Vancouver

Liu W. Techniques for Leakage Power Reduction in Nanoscale Circuits: A Survey. Informatics and Mathematical Modelling, Technical University of Denmark, DTU, 2007.

Author

Liu, Wei / Techniques for Leakage Power Reduction in Nanoscale Circuits: A Survey.

Informatics and Mathematical Modelling, Technical University of Denmark, DTU, 2007.

Publication: Research - peer-reviewReport – Annual report year: 2007

Bibtex

@book{4999085a5f4f4d3bb7b2c8defc984bd9,
title = "Techniques for Leakage Power Reduction in Nanoscale Circuits: A Survey",
author = "Wei Liu",
year = "2007",
publisher = "Informatics and Mathematical Modelling, Technical University of Denmark, DTU",

}

RIS

TY - RPRT

T1 - Techniques for Leakage Power Reduction in Nanoscale Circuits: A Survey

AU - Liu,Wei

PY - 2007

Y1 - 2007

N2 - This report surveys progress in the field of designing low power especially low leakage CMOS circuits in deep submicron era. The leakage mechanism and various recently proposed run time leakage reduction techniques are presented. Two designs from Cadence and Sony respectively, which can represent current industrial application of these techniques, are also illustrated.

AB - This report surveys progress in the field of designing low power especially low leakage CMOS circuits in deep submicron era. The leakage mechanism and various recently proposed run time leakage reduction techniques are presented. Two designs from Cadence and Sony respectively, which can represent current industrial application of these techniques, are also illustrated.

M3 - Report

BT - Techniques for Leakage Power Reduction in Nanoscale Circuits: A Survey

PB - Informatics and Mathematical Modelling, Technical University of Denmark, DTU

ER -