Static Routing in Symmetric Real-Time Network-on-Chips

Publication: Research - peer-reviewArticle in proceedings – Annual report year: 2012

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With the rising number of cores on a single chip the question on how to organize the communication among those cores becomes more and more relevant. A common solution is to use a network-on-chip (NoC) that provides communication bandwidth, routing, and arbitration among the cores. The use of NoCs in real-time systems is problematic, since the shared network and all cores connected to it have to be analyzed to derive time bounds of real-time tasks.

We propose to use a statically scheduled, time-division-multiplexed NoC design that allows a decoupled analysis of individual real-time tasks. Our network provides virtual circuits between all cores. These virtual circuits are implemented by delivering messages periodically on a static, fixed routing schedule. Since the routing does not change, it can be pre-computed offline.

This work focuses on the computation of routing schedules for symmetric NoC topologies, e.g., torus and hyper-cube. Due to the symmetry, the all-to-all communication can be modeled via simplified communication patterns that are concurrently processed by all routers. The scheduling problem is solved by a heuristic that tries to maximize the overlap of active patterns. Our experiments show that, for larger networks, our heuristic yields schedule lengths that are only 15% to 20% longer than theoretical lower bounds.
Original languageEnglish
Title of host publicationProceedings of the 20th International Conference on Real-Time and Network Systems (RTNS 2012)
PublisherAssociation for Computing Machinery
Publication date2012
Pages61-70
ISBN (print)978-1-4503-1409-1
DOIs
StatePublished

Conference

Conference20th International Conference on Real-Time and Network Systems (RTNS 2012)
CountryFrance
CityPont à Mousson
Period08/11/1209/11/12
Internet addresshttp://rtns2012.loria.fr/
CitationsWeb of Science® Times Cited: No match on DOI
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