Scheduling with Bus Access Optimization for Distributed Embedded Systems

Publication: Research - peer-reviewJournal article – Annual report year: 2000

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Scheduling with Bus Access Optimization for Distributed Embedded Systems. / Eles, Petru; Doboli, Alex; Pop, Paul; Peng, Zebo.

In: IEEE Transactions on VLSI Systems, Vol. 8, No. 5, 2000, p. 472-491.

Publication: Research - peer-reviewJournal article – Annual report year: 2000

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Author

Eles, Petru; Doboli, Alex; Pop, Paul; Peng, Zebo / Scheduling with Bus Access Optimization for Distributed Embedded Systems.

In: IEEE Transactions on VLSI Systems, Vol. 8, No. 5, 2000, p. 472-491.

Publication: Research - peer-reviewJournal article – Annual report year: 2000

Bibtex

@article{cb6740cd53fb48149bcb5e647191e3f3,
title = "Scheduling with Bus Access Optimization for Distributed Embedded Systems",
publisher = "I E E E",
author = "Petru Eles and Alex Doboli and Paul Pop and Zebo Peng",
year = "2000",
doi = "10.1109/92.894152",
volume = "8",
number = "5",
pages = "472--491",
journal = "IEEE Transactions on VLSI Systems",
issn = "1063-8210",

}

RIS

TY - JOUR

T1 - Scheduling with Bus Access Optimization for Distributed Embedded Systems

A1 - Eles,Petru

A1 - Doboli,Alex

A1 - Pop,Paul

A1 - Peng,Zebo

AU - Eles,Petru

AU - Doboli,Alex

AU - Pop,Paul

AU - Peng,Zebo

PB - I E E E

PY - 2000

Y1 - 2000

N2 - In this paper, we concentrate on aspects related to the synthesis of distributed embedded systems consisting of programmable processors and application-specific hardware components. The approach is based on an abstract graph representation that captures, at process level, both dataflow and the flow of control. Our goal is to derive a worst case delay by which the system completes execution, such that this delay is as small as possible; to generate a logically and temporally deterministic schedule; and to optimize parameters of the communication protocol such that this delay is guaranteed. We have further investigated the impact of particular communication infrastructures and protocols on the overall performance and, specially, how the requirements of such an infrastructure have to be considered for process and communication scheduling. Not only do particularities of the underlying architecture have to be considered during scheduling but also the parameters of the communication protocol should be adapted to fit the particular embedded application. The optimization algorithm, which implies both process scheduling and optimization of the parameters related to the communication protocol, generates an efficient bus access scheme as well as the schedule tables for activation of processes and communications.

AB - In this paper, we concentrate on aspects related to the synthesis of distributed embedded systems consisting of programmable processors and application-specific hardware components. The approach is based on an abstract graph representation that captures, at process level, both dataflow and the flow of control. Our goal is to derive a worst case delay by which the system completes execution, such that this delay is as small as possible; to generate a logically and temporally deterministic schedule; and to optimize parameters of the communication protocol such that this delay is guaranteed. We have further investigated the impact of particular communication infrastructures and protocols on the overall performance and, specially, how the requirements of such an infrastructure have to be considered for process and communication scheduling. Not only do particularities of the underlying architecture have to be considered during scheduling but also the parameters of the communication protocol should be adapted to fit the particular embedded application. The optimization algorithm, which implies both process scheduling and optimization of the parameters related to the communication protocol, generates an efficient bus access scheme as well as the schedule tables for activation of processes and communications.

UR - http://www2.imm.dtu.dk/pubdb/p.php?4620

U2 - 10.1109/92.894152

DO - 10.1109/92.894152

JO - IEEE Transactions on VLSI Systems

JF - IEEE Transactions on VLSI Systems

SN - 1063-8210

IS - 5

VL - 8

SP - 472

EP - 491

ER -